Blake,
Read this and tell me if it sounds like NSM's Jalapeno chip is embedding RDRAM? It states, "Cyrix has also designed a Rambus interface directly onto the die."
Your response or clarification would be appreciated.
MileHigh
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National/Cyrix
Brian Halla, chairman, president, and chief executive of National Semiconductor Corp., Santa Clara, outlined Cyrix's roadmap, which centers around next year's introduction of the MediaPC, a "PC-on-a-chip" for the ultra-low-cost PC market. The 233- to 300-MHz device integrates an MPU, a video decompression engine, 2D graphics, and associated peripheral logic.
Also in 1999, Cyrix will ship the MXi, a slightly more expensive chip based on the Cayenne core that Cyrix will ship shortly. Cayenne adds a second MMX unit to Cyrix's M II design, as well as the 3DNow! multimedia instructions developed by AMD and Cyrix. The MXi will run at 333 MHz to over 400 MHz.
Finally, Halla confirmed EBN's earlier report that National will still pursue the Socket 7 market with Jedi, an MXi-style processor family designed for Socket 7. Jedi is actually a separate program within Cyrix that will apply the Cayenne core "cost-effectively to the Socket 7 market," said Stan Swearingen, vice president of PC products for Cyrix, Richardson, Texas.
In 2000, National will introduce its next-generation core, code-named Jalapeno, which will be designed as a discrete chip running at over 600 MHz and manufactured on a 0.18-micron pro-cess. The chip will integrate 256 Kbytes of L2 cache on the die. To minimize the need to access both the L1 and L2 cache, Cyrix has also designed a Rambus interface directly onto the die.
Cyrix's high-end processor, dubbed M3, will combine 3D graphics and the Jalapeno core beginning in the fourth quarter of 1999, according to Greg Grohoski, an engineer with Cyrix.
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