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Politics : Formerly About Advanced Micro Devices

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To: Tenchusatsu who wrote (39658)	10/20/1998 9:35:00 AM
From: Ali Chen	Read Replies (1) of 1578938

Ten, <Every CPU benchmark shows that the P6 is superior to the K6 in integer instructions... the K6 wasn't as efficient as the P6 in integer execution. the K6 practically needs a larger L1 cache because of its lack of backside L2 cache.> Wrong statements. Too generic. K6 lacks NOTHING. It is Intel's north bridge that has a cheap "lookaside" L2 cache architecture and lacks an independent memory bus. It is a matter of Intel's system implementation, cheap implementation. It has very little to do with K6 internal merits. K6 beats P-II on every benchmark at low core frequencies, where the "Intel architecture" P5-class memory subsystem become more balanced with K6 core capabilities (relative memory latencies become smaller). You forgot the simple fact that AMD had no resources to change the P5-Intel-dominated infrastructure of the whole PC industry, and has to play within the P5 rules. <but you're not going to convince people who know a little better.> I'm sorry, but it is certainly not you. Brian's argument about cacheless Celeron is perfectly valid.

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