Re: "Bad news Elmer. There's no on chip L2 for one good reason: when the K7 comes out, nothing Intel has will be able to touch it. So why bother increasing the performance even more? 128k L1, 1/2 speed L2, and 200 MHz EV/6 bus (not to mention the monster K7 core) are more than enough to blow any sixth generation Intel design derivation off the map."
It's amazing what the fathfull will believe. I know better. AMD is leaving out the L2 because they can't manufacture the K7 with it on the die, plain and simply. And AMD will pay a huge price.
When Intel added L2 to the Celeron die, they eliminated a large number of pins for the backside bus. They also slowed down the top frequency the tester had to run at. In the past, the tester had to run at the speed of the backside bus, or half that speed. Now Intel gets by with cheap testers with reduced pin count and only the need to run at 100mhz for the front side bus. So far, AMD has gotten by with a generation of testers that only needed to run at 100mhz for the K6 FSB. The K7 will require an entirely new highspeed generation of testers with very high VERY expensive pincount, just because of the lack of on die L2. By your claim, AMD is saving money in die cost but facing an enormous capital investment of many many 10s of $$$millions$$ if not 100s of $$$millions$$$ just to test the BSB. If you think manufacturing cost is a simple function of die area it shows why you buy AMD's balony. Intel had confidence in their process and made the decision to add L2. They pay a little more for silicon but they save a lot in manufacturing. Cheaper package, cheaper testing, no SRAM interface, no added SRAM. For the K7 the manufacturing costs will be very high and the choked down slowed down BSB will choke performance on real silicon but you'll be happy to hear, it should have no slowdown on press releases.
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