October 26, 1998, Issue: 1032
Section: News
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But rivalry between built-in self-test and automatic test equipment appears to cool -- Memory-test war flares at global conference
Stan Runyon
Washington - Evidence of a full-fledged memory-test war emerged here at last week's International Test Conference as ATE vendors rushed to satisfy the lofty speed and accuracy needs of such emerging DRAM architectures as Rambus. Given the investment necessary to field the required test equipment-even before it is clear which of the new memory types will win out for the coming round of PC architectures-the casualties could be heavy.
Advantest, Hewlett-Packard, Schlumberger and Teradyne have all announced or begun to ship machines to Rambus Inc. and other memory manufacturers. Following Intel's lead in endorsing Rambus Inc.'s Direct RDRAM architecture, almost all leading DRAM vendors have announced plans to ship Direct RDRAMS next year. Compaq, Dell and Hewlett-Packard, among others, have said they are designing new PCs centered on RDRAMs as the main memory.
Even as the memory-test war breaks out, the ATE and BIST communities appear to have achieved armistice in the interest of hammering out workable test solutions for systems-on-chip. At last week's International Test Conference here, several suppliers of automatic test equipment and built-in-self-test solutions acknowledged that system-on-chip test calls for both BIST and ATE and that neither camp could do the job alone. To that end, Credence Systems, LogicVision, Opmaxx and others disclosed outwardly friendly partnerships that, for now, establish a cease-fire.
On the memory front, the first Rambus parts on the horizon and are expected to work out of the chute at data rates of 800 Mbits/second-way beyond the capability of the present crop of memory testers. Shortly thereafter, the Rambus road map will lead to 1-Gbit/s parts and beyond.
Thus, the weapons of choice in the memory-test skirmishes are machines that promise gigabit data rates and sub-nanosecond accuracies at the device pins. Such performance is easier to achieve in engineering characterization than in the harsher environments and competition-driven high throughputs found on production floors.
To remove heat and hold accuracy, for example, test heads must be liquid-cooled. To maintain the fast edges at the device pins, the part under test must be located as close as possible to the pin electronics in the test head.
ATE vendors have come up with a variety of solutions, each claiming superiority for its methodology. Hewlett-Packard came to the conference to roll out the HP 95000, which deploys its Gbit technology (with < 1-ns pulsewidths) built into a tester-on-a-chip approach. By shrinking much of the pin electronics into a proprietary chip, HP is able to provide multisite testing-a crucial requirement for memory test-of up to 16 devices at once.
Gaylord Erickson, product-marketing manager at HP's California Semiconductor Test Operation, claimed the test cell with combined handler consumes about one-third the floor area of competing units. The HP tester uses a high-tech water-cooling system at the head. The machine can test both a memory core and embedded logic in a single pass.
Advantest-the acknowledged market leader in memory test, with about 65 percent of the market-fielded the 1-GHz, eight-site T5591 Rambus tester to handle "the next 18 months of business, because we cannot afford to miss a step," said marketing manager Gary Fleeman. "We'll have a 64-site solution as soon as the market demands it. Remember, the new memories are a gray area right now."
The overall test accuracy of the water-cooled T5591 is 60 ps, with 20 ps of jitter. The tester hooks to Advantest's own handler, eliminating questions of responsibility for equipment problems and maintenance. Some competing testers are hooked to commercially available handlers.
Schlumberger Automated Test Equipment came to the conference to launch the liquid-cooled, eight-site, 1-Gbit/s DX2200, a high-accuracy unit for production testing of Direct RDRAM, SSRAM and RIMM modules. Product manager Chris Mack said the unit provides full functional testing in a single insertion, the ability to dock to e-beam systems, and an accuracy-assurance system, called AutoEdge, that provides "+50-ps edge placement accuracy."
Teradyne, which offers its J973 800-Mbit/s unit for Direct Rambus testing, "is going to 1-Gbit/s next year, and our goal is to go beyond the Rambus road map," said marketing manager Rod Stewart. He said the goal is to test integrated products with surrounding logic in a single insertion. "The packetized system in Rambus calls for different kinds of software, and don't forget that even though people may put Rambus on a slow chip, they'll have to deal with the fast interface."
Teradyne's cooling solution is a hybrid one: water for the mainframe and a dielectric liquid that evaporates at room temperature (in case of leaks) for the cold plates at the test head.
Comrades in arms
Tensions are easing in BIST/ATE as erstwhile opponents become allies to conquer test-resistant systems-on-chip. Such major test vendors as Credence, Hewlett-Packard, LTX and Teradyne now admit that embedded memories and a lack of test access call for new test methods that combine the best of BIST and external ATE. And LogicVision-once the most visible proponent of all-BIST solutions-now concedes that embedded ATE must include some external tester support.
To do that, LogicVision said it will team with Credence to develop and market products linking LogicVision's embedded-ATE solutions with Credence's semiconductor-test systems. "It's the only way to satisfy users' demands for dramatically lower test costs and shortened time-to-volume," said Michael Howells, LogicVision vice president of engineering.
"Embedded ATE lets external ATE test system-on-chip devices cost-effectively," said Jerry Hutcheson, chief executive of VLSI Research Inc.
Credence chief executive Bill Bottoms, meanwhile, revealed partnerships with Opmaxx that, along with technology acquired from HPL, TSSI, Zycad and the new LogicVision arrangement, "will put Credence into a new era of test in which we can offer users capabilities for on-chip analog, digital, memory and RF functions. We can help them partition test requirements into the most effective solution."
Bottoms also revealed an approach: built-off self test (BOST). The method offloads on-chip BIST and puts those resources-in the form of a device-specific BIST engine on a custom chip-on the load board next to the chip under test. The idea is to retain the advantages of memory BIST but avoid taking precious area from the chip under test and, at the same time, sidestep the lack of reprogrammability of the test once it is fabricated on the device.
"BIST alone says a part is broken but not why," Bottoms said. "BIST and ATE can do both. And as the semiconductor industry, however it is redefined, enters the third phase of its historical development-in which system-driven designs will dominate-BOST offers the best economics."
Copyright ® 1998 CMP Media Inc.
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