Tench,
Here's some info on k7, die size, cache sizes and 8-way Multi-processing.
Of course Tench you are the server expert and maybe it's all vaporware. Like you I tend to discount their likely success for MP servers (at least in 99). I do expect it to be very successfull in high end PC/ engineering workstation markets.
Just my thoughts.
Kash:
:
News September 25, 00:45 Eastern Time
Oct. 24, 1998 (Electronic Buyers News - CMP via COMTEX) -- Silicon Valley- After years of watching Intel Corp.
break trail in the chip market, Advanced Micro Devices Inc., Cyrix Corp., and other chip makers used the
Microprocessor Forum in San Jose last week to strike out in new directions.
When Intel chose to outline its chip plans a week before the forum, it cleared the way for "clone" processor
makers to describe their own unique chip and bus designs, including a new part by start-up Rise Technology Co.
AMD described its forthcoming K7 chip, which not only will use the EV-6 system bus licensed from Compaq
Computer Corp.'s Digital Equipment Corp. subsidiary, but will be the first seventh-generation CPU from any chip
maker.
"With the K7, AMD moves into uncharted territory," said analyst Linley Gwennap of Sebastopol, Calif.-based
MicroDesign Resources Inc. (MDR), which hosted the show.
Although the positioning against Intel has become almost a cliche, Intel's high-profile push into the 64-bit space
forced even RISC vendors like Digital to apply a marketing spin to details of the 21364, the next-generation Alpha
chip. Motorola Inc., however, chose to ignore Intel in presenting the G4, its first PowerPC chip to include the
AltiVec multimedia instructions.
Advanced Micro Devices
Sunnyvale-based AMD surprised the audience when it announced that the EV-6 bus architecture it licensed from
Digital for use with its forthcoming K7 microprocessors will run at 200 MHz, much faster than the 133-MHz bus
speed Intel has proposed.
The K7 is still on track to ship in the first half of 1999, with supporting chipsets from both AMD and third parties,
Meyer said. The device will support off-chip Level 2 cache sizes from 512 KB to 8 MB, and the EV-6 bus can
handle multiprocessing systems of eight K7s in parallel, said Michael Steele, product marketing manager for
AMD's Computation Products Group.
The K7 may have one obstacle, however-an estimated die size of 184 sq. mm, with manufacturing done on a
0.25-micron process. But AMD's Meyer said the K7's die size is equivalent to the size of the original K6, and that
the next-generation chip should shrink to under 100 sq. mm when AMD begins 0.18-micron production in Dresden,
Germany, around 2000.
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