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Politics : Formerly About Advanced Micro Devices
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To: RDM who wrote (40507)10/31/1998 2:02:00 PM
From: Scumbria  Read Replies (2) of 1573712
 
RDM,

When evaluating on-chip cache the speed difference between the cache fill rate and the cpu rate is of critical importance.

This is nonsense. The cache fill rate is determined by the speed of the dram.

The key performance factor for Winstone type benchmarks is memory latency, which is rapidly become constrained by sram speeds for L1 and L2 hits. That is why we are starting to see designs (like K7) which have multi-cycle L1 latencies.

Scumbria
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