Re: "EP, <The P2P bus is of very questionable benefit>
You and your buddies at Intel seem to have missed
one more inflection point in modern technology:
the time for old "busses" is over! By applying the
whole power of your deduction, you may find out that
the EV6 P2P is NOT a BUS, it is POINT-TO-POINT
connection, and EXTREMELY FAST, without any
tracing/termination/anti-reflection tweaks
(where the major system production cost sits).
The busses/switches are going into SILICON, buddy,
S-I-L-I-C-O-N, to spell out for you, where they can
really do the intercommunication job, with
greater potential for speed, and without Xeon's
2-to-4 scalability constipation."
Ali, you're just getting more and more confused as time goes by. Your point about P2P not being a bus is correct, it is Point to Point, but you can't go from the processor to the chipset in silicon alone. The chipset will require additional pins and traces for each processor added to the system. Will there be 1 chipset for a single processor system, another for a 2 processor system and still another for a 4, 8 etc? This added pincount is very expensive. K7 is stuck with very high, expensive pincount, expensive chipsets possibly with multiple versions, and a virtually untestable BSB (unless AMD slows it down).
All these problems go away for Intel. The Intel P6 bus has none of these problems. No expensive added pins needed for P2P. With large cache, the bus does not saturate below 4 processors and there is no limit in sight for the bus frequency. On die L2 means no need to test at full core speed which is rapidly becoming beyond the state of the art in manufacturing equipment. The on die L2 greatly reduces processor pin count, reducing packaging cost and equipment cost and increasing performance. The K7 however does have very nice foils.
Perhaps some more ruffage in your diet might help loosen you up.
EP |
