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Politics : Formerly About Advanced Micro Devices

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To: Petz who wrote (40659)	11/2/1998 1:12:00 PM
From: Tenchusatsu	Read Replies (1) of 1573954

<Ten, it would seem to be a good idea for Intel to make a server chip out of the Mendocino core. They could integrate 512K or 1M of half speed L3 (much cheaper than full speed), or full speed L3, into a Slot 1 or 2 cartridge. Wouldn't the reduction in bus traffic due to the internal 128K L2 improve 2 and 4 way server performance?> What you are suggesting is adding a layer of on-die L1.5 cache between the L1 and L2 caches of Xeon. Unfortunately, this has no effect on front-side bus traffic, unless you also increase the L2 cache size. Adding the L1.5 cache only reduces back-side bus traffic. While this may increase performance somewhat, I'm sure Intel decided the ROI wasn't worth it, at least for the P6 core. Tenchusatsu

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