Client Server News Nov 2
Chip Expert Rates
Merced a Weak Sister
In the wake of the Microprocessor Forum and all
that was revealed there, the Microprocessor Report
concludes that "either the McKinley implementation
is extremely good, or the Merced implementation
is extremely poor. We think the answer lies some-where
in the middle, but closer to the latter extreme."
It suspects that the Merced may be so disadvantaged as
to make it "mainly a software development vehicle for
McKinley."
The newsletter is unsettled by the fact that Forster's
core Ð the IA-32 chip that's supposed to appear six
months after Merced in late 2000, early 2001 (CSN No
270) Ð will deliver the same performance as the 64-bit
Merced's and says that means that "either IA-64 has
no advantage over x86 or that Merced's implementation
weaknesses are larger than IA-64's advantages."
It notes that the "Merced core will achieve lower clock
speeds and is probably physically larger than the
Forster/Williamette core, again indicating inherent
inefficiencies in the Merced design." It also says that
since Forster's is better, "Merced's lack of system
bandwidth is potentially embarassing." Merced, it
reckons, will do better than Forster only on applications
that take advantage of the 64-bit addressing. It,
therefore, concludes that "if Forster carries a lower list
price than Merced, it could discourage Merced's adoption
in servers."
Otherwise, a few more bits and pieces emerged at
the forum about Merced although Intel is still playing
coy about such basics as clock speed, pipeline and system
bus:
° x86 compatibility is through an IA-32 decoder.
IA-32 and IA-64 instructions are stored in a single
instruction cache and when fetched are routed through
either an IA-32 or IA-64 decoder. That way, x86
instructions can avail themselves of IA-64's speed
such as its fast floating point.
° Unlike its McKinley follow-on, which is supposed
to carry big on-chip caches, Merced has little on-die
cache though Intel didn't say exactly how much. The
Microprocessor Report figures it for 256K and
McKinley's for 2MB. Given that Intel said Merced
will do more than 10 Gbytes/s to the external cache
and figuring on a 128-bits wide interface, it puts CPU
speed at over 625MHz though the newsletter is expecting
first shipments to operate at 700MHz-800MHz.
° Madison, the 0.13 McKinley shrink, due by 2002,
maybe earlier, for high-end workstations and servers
could achieve 1.6GHz and could carry 4MB of on-chip
cache. Deerfield, Madison's price-conscious alternative
for volume workstations and servers, might carry
1MB and a "different bus interface to reduce cost."
Priced at what the cheapest Xeon goes for today, that
means that "IA-64 could ease into the high-end PC
market as early as 2002." |
