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Politics : Formerly About Advanced Micro Devices
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To: Paul Engel who wrote (41192)11/10/1998 6:18:00 PM
From: Scumbria  Read Replies (1) of 1571249
 
Paul,

My guess is that the L3 cache refers to an external cache and the L3 cache controller would somehow default to the Chip Set cache controller (L2 becomes L3) ?

The external cache controller does not need any knowledge of what is going on inside the CPU. It sees a series of reads and writes coming across the Socket 7 bus, and responds to them. The name L2, L3 or whatever is irrelevant to the design.

Assuming the voltages are the same, the only required difference between a K6-2 and K6-3 motherboard would be a BIOS which recognizes the K6-3 CPUID.

Scumbria
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