Electronica: Fujitsu demos MPEG-2 decoder
By Junko Yoshida
EE Times
(11/10/98, 4:14 p.m. EDT)
MUNICH, Germany — Fujitsu Mikroelektronik GmbH, showed off Fujitsu's first MPEG-2 Main Profile @ High Level decoder chip at Electronica this week. The device was developed in partnership with Heinrich-Hertz-Institute (HHI) of Berlin, which provided the algorithm for the chip.
The commercially available HiPEG MPEG-2 decoder, which was developed as an ASIC, started life “as a pure research project with HHI more than two-and-a-half years ago to demonstrate how our ASIC technology can handle such a complex algorithm on a single chip,” said Guenther Junge, ASIC marketing manager at Fujitsu Mikroelektronik (Dreieich-Buchschlag, Germany). In the course of the project, “we recognized that this can be a significant chip that Fujitsu can sell both in the U.S. and Japanese markets,” Junge said.
The HiPEG decoder is capable of decoding all 18 video formats specified by the U.S. Advanced Television Systems Committee (ATSC), and any video streams up to1,440 progressive and 1,920 interlaced technology. The device can handle picture frequencies of both 50 Hz (required for Europe) and 60 Hz (required for the United States). The HiPEG chip also provides a 3/2 pull-down feature, but as a pure decoder, and it does not come with a display processor.
“There is still a lot of room for our product to play,” Junge said, even as a number of U.S., European, Japanese and Korean companies have rushed to launch high-definition decoder chips. “Many companies have made a lot of announcements on their product plans, but the only commercial MPEG-2 MP@HL ICs out on the market today are those by LG Semicon, STMicroelectronics and Mitsubishi/Lucent,” he said. “To make an HD decoder with such complexities without bugs is not an easy task.”
Fujitsu's chip has already won a design-win in a U.S. professional video product, Junge said.
To bring the chip down to a consumer market, Fujitsu and HHI need to develop a more highly integrated chip that uses less memory and consumes less power. The HiPEG chip demonstrated Tuesday (Nov. 10) at Electronica was made in a 0.35-micron CMOS process and uses 128 Mbit of SDRAM. It operates on a 3.3-volt supply and dissipates 2.5 watts of power. The chip, shown on a demonstration board, was encased in a heat-sync package with a fan.
Fujitsu plans to introduce a newer version of HiPEG built in a 0.25-micron process and integrating a demux capability by April 1999.
Back in Japan, Fujitsu is separately preparing a dedicated audio DSP capable of handling 15 different audio decoding algorithms, Junge said. “Our plan is to integrate the audio DSP into HiPEG some time later next year.”
Fujitsu expects to use a 0.25-micron DRAM-logic process to integrate DRAM right into the HiPEG chip by mid 2000, according to Fujitsu's product road map.
HHI will need to develop a new algorithm for Fujitsu's future consumer-friendly HiPEG solution
eetimes.com |
