Katherine, I would like to respond to one of you comments:
>>On these points, I believe you are somewhat mistaken. 0.25 micron devices are here now, and 0.18 is rapidly approaching. OPC and/or phase shift masks are required to print these feature sizes using 248 nm light. At the end of 1997, Intel predicted 60% of their total capacity (total, not new construction) would be at 0.25 micron or smaller by the end of 1999, and shrinks are actually proceeding much more quickly than anticipated. Other companies are following similar trends.
High end masks also account for a disproportionate share of mask company profits. Less advanced masks suffer from commodity pricing, while the more advanced masks do not.>>
With regard to the Intel prediction, only the critical layers in their .25 micron process require .25 micron masks. You make it sound like all their masks are at .25 micron. Their process technology is proprietary but I will make an assumption based on my days in the fab. Their .25 micron process requires maybe 15 or 20 masks. Out of these I will guess that 3 or 4 are critical layers and require .25 micron masks. The other layers have looser design rules and do not use leading edge masks. So in a given mask set, maybe 20% at most are leading edge masks.
Most of Intels production, and the lions share of their profits, comes from CPUs (pentium). This is a large chip (one of the largest in the industry) and Intel has a big incentive to shrink it to the smallest possible size to increase the die per wafer. Their incentive to shrink is even greated with the delay in going to 300mm wafers. Not only are there a small number of pentium devices on the market (small number of mask sets), but Intel makes their own masks. Based on these facts, I don't think it is fair to use Intel as an example of the macroeconomics affecting the mask industry. The economics of die shrinks probably influence Intel more than any other semiconductor company. Yes, the industry is going to .25 and below, but with the current level of overcapacity most fabs do not have a huge incentive to get more die per wafer, i.e. increase their production. I think the race to smaller geometries will pick up when ASPs pick up. That will only happen when the excess capacity is out of production across the industry. We are not there yet. |
