>>It does nothing, however,
to affect my analysis that MASK is significantly undervalued. Remember, PLAB
and DPMI are already trading at twice the valuation of MASK and the Asian
rebound that would justify such valuations is hard to find.<<
I'm not arguing about MASK's undervaluation. I really haven't looked at the situation closely enough to have an opinion one way or the other. At the same time, my general investing philosophy is that buying market leaders is a more successful strategy than buying undervalued stocks. Reasonable people may disagree, but that's how I invest my own money. (Though not in DPMI, MASK, or any other semi supplier company, for ethics reasons I've already discussed elsewhere.)
>>"foundries use orders of magnitude more
masks than dedicated fabs."<<
According to Dataquest, ASICs account for 30% of the total mask market. The lifetime of an ASIC mask ranges from a few dozen to a few hundred wafers, while a DRAM mask will be used for several (5-10? I don't remember) thousand wafers. So maybe "orders of magnitude" was an exaggeration. Still, since foundries are mostly in Asia, the Asian region uses more masks for a given unit volume.
news.semiconductoronline.com
>>It is hard to
conceive of a rebound in Asia that is not part of a generalized industry rebound.<<
I'd actually put it a different way: It's hard to conceive of a general industry rebound without a rebound in Asia.
>>For the bulk of the industry, going from say, .35 to .25 or, especially,
from .25 to .18 is not an economically or financially correct move in the present
environment. The reasons for this slowdown are the same as the reasons for the
slowdown in the transition to 300mm wafers, for example. <<
The economics of a shrink are NOT the same as the economics of a wafer size transition. A shrink gives you more capacity AND faster chips with more transistors on them, while costing relatively little money. For a shrink, you have to buy new masks ($50,000 for the set), and maybe steppers ($6-10 million apiece), but not much else. A wafer size transition only adds capacity, and requires a new fab ($3 billion, minimum) with a new equipment toolset.
In addition to Intel, evidence of accelerated shrinks includes all the announcements from DRAM makers of accelerated 64M chip introductions, and announcements from several foundries that 0.25 micron processes are commercially available. A small sampling of links follows:
TSMC Sees Broad-Based Momentum in 0.25 Micron Demand; Fast Ramp to High Yields
news.semiconductoronline.com
Virtual Silicon and Amkor Jointly Offer Second-Generation 0.25 Micron COT Solutions
news.semiconductoronline.com
VLSI VSC9 0.25-micron ASIC Process Fully Operational; VSC10 0.2-micron Process on Schedule; Copper Interconnect Slated for Next-Generation 0.15-micron Process
news.semiconductoronline.com
Apologies to anyone offended by the profusion of links from my own site. These links are to press releases, but I can get things out of the search engine faster than Yahoo.
Katherine |
