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Politics : Formerly About Advanced Micro Devices

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To: Elmer who wrote (41521)	11/16/1998 2:09:00 AM
From: Scumbria	Read Replies (1) of 1574306

Elmer, It would seem that putting the L2 cache off chip is not the best solution from a performance standpoint unless it would be accessible just as though it were on chip. This should have minimal performance impact for K7. Remember that K7 has a 128K L1 (4X the size of the current Xeon's and PII's.) A few clocks extra latency going off chip for L1 misses will not be devastating to performance. Obviously it would be better to have the L2 onboard, but the large L1 will nullify most of the impact. If AMD goes 64 bit then it will effectively cut the bandwidth in half. Bandwidth from the L2 is not very important for performance of single processor systems. Data is only moved one cache line at a time, never in large blocks which would make the bandwidth a significant factor. Scumbria

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