<Ten, just to clear out our discussion about AMD K7 point-to-point vs. Xeon's shared bus. Read up:>
Ali, there's no doubt in my mind that point-to-point has its advantages. We've been over the advantages and disadvantages countless times.
The problem is that in the K7 platform, I just don't see the point (no pun intended) behind the point-to-point connections. Xeon buses are not overloaded even with full 4-way configurations, and this holds true even if the L2 cache size per processor is at the minimum 512K. That's pretty good for a "mediocre" 100 MHz bus speed.
Now considering that the K7 is going to be like a P6 with a few extra cylinders, there's no way that the K7's appetite for data is going to be that much bigger than the P6. Plus, that P2P connection doesn't include a direct path to memory like some implementations of Alpha. That's why the value of P2P in K7 is questionable, when a simpler bus architecture would have sufficed. Perhaps the K7 architects are much more forward-looking, but more realistically, AMD had no choice in the first place considering that they had to borrow Digital's EV6 platform.
As for the value of P2P in I/O buses like NGIO, I have no comment at the time, since I haven't had the time to look at the NGIO specs.
<It looks like the concealed copying is still at habit over there (just joking, as usual!) And they didn't tell even you, a loyal employee... Geez, what a company...>
There's a lot of things that Intel doesn't tell me, a loyal employee, mainly because I'm not paid to know them, and even if I were, I wouldn't be telling you, either. But I can tell you that there's a lot of things that I *do* know that blind AMD supporters wouldn't and shouldn't know, such as juicy details on the @&*#($&&*#& ...
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The remainder of this message has been intercepted by Intel intelligence. Have a nice day.
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