>>Just one quick question---is the new chip by Transmeta any threat to Rambus?
Discussion on Intel thread (if this helps any)---Ed:
Jock - Re: "any comments on the potential threat to Intel's hegonomy that the new chip from Transmeta poses?"
Transmeta has been working many years and still hasn't got their first chip completed.
Meanwhile, Intel is designing at least 6 or advanced CPUs, chips sets to go with them, graphics chips, etc.
Intel also has the fab capacity to make >100,000,000 CPUs per year and will be introducing 0.18 micron versions of their processors by mid 1999 - possibly a bit sooner.
TransMeta will make as big an impact as IDT's WinCHIP - maybe even bigger.
Paul
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Jock,
Here's a quote from the article that you linked to:
<The upshot is this: sections of the patent (No. 5,832,205) discuss a chip that can translate Intel chip instructions into a more advanced format referred to as VLIW (Very Long Instruction Word). VLIW is a catch-all term for a variety of technologies that essentially combine many simple computer instructions into a single long instruction which can then be executed more efficiently and quickly than current computer code.>
This looks a lot like Merced. As we all know, Merced can translate legacy x86 instructions (now known as IA-32) into the new IA-64 instructions. IA-64 is called EPIC technology (Explicitly Parallel Instruction Computing), and it similar to the VLIW technology that Transmeta seems to be pursuing.
<GEEK MODE ON>
I know of two problems with VLIW: code bloat and little flexibility for future CPU designs. The first problem could probably be solved via brute-force buffering, much like AMD's K7 CPU. The second problem is especially tough because the structure of VLIW instructions depends heavily on the execution unit structure within the CPU core. This means that to go from one generation of VLIW to the next, you'll have to recompile your code. I think Transmeta may be using the IA-32 to VLIW translation as an abstraction layer to solve the second problem. Thus, the VLIW core can be interchanged between CPU generations without require code recompiling, thanks to that translation layer.
<GEEK MODE OFF>
The big catch is that Merced's compatibility with IA-32 serves mainly to "grease the skids" to IA-64, Intel's new direction for servers, and perhaps for high-end desktops in the mid-future. But Transmeta's design is geared exclusively towards IA-32 execution, so potentially it could do better than Merced on IA-32 code. It remains to be seen whether Transmeta's approach to CPU design is actually faster than Intel's upcoming Willamette (P7) core. My guess is that it won't.
In conclusion, right now, Transmeta looks more like a cool engineering project than a threat to Intel. The Transmeta design looks neat in theory, but in practice, who knows?
Tenchusatsu
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potential threat to Intel's hegonomy that the new chip from Transmeta poses?
As much as the PowerPC chip did?
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Ten,
<The upshot is this: sections of the patent (No. 5,832,205) discuss a chip that can translate Intel chip instructions into a more advanced format referred to as VLIW (Very Long Instruction Word). VLIW is a catch-all term for a variety of technologies that essentially combine many simple computer instructions into a single long instruction which can then be executed more efficiently and quickly than current computer code.>
This looks a lot like Merced. As we all know, Merced can translate legacy x86 instructions (now known as IA-32) into the new IA-64 instructions. IA-64 is called EPIC technology (Explicitly Parallel Instruction Computing), and it similar to the VLIW technology that Transmeta seems to be pursuing.
VLIW simply places a group of instructions into a predictable position for parallel decoding (and possibly parallel execution.)
The reason that Merced does the x86->VLIW translation is because it has too, not because there is any performance advantage. The value of VLIW in Merced is for native IA64 compiled code. Transmeta is not doing anything to the compiler. They are simply converting each x86 instruction into a fixed set of parallel smaller instructions. I'm not sure what the value is to doing this since most x86 instructions are read-modify-write, which obviously can't be executed out of order.
If all they have to offer is this idea, I won't be holding my breath waiting for TransMeta to take over the x86 world.
Scumbria
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Re: Transmeta and Merced
You explained it better than I could. Like you said, it's hard for me to see the value of translating x86 instructions into VLIW. A conventional out-of-order RISC core like P6, K6, and K7 would be much better suited toward uncovering the instruction-level parallelism within the legacy x86 architecture.
Tenchusatsu
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