Formerly About Advanced Micro Devices Message Board

STOCKTALK

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor. We ask that you disable ad blocking while on Silicon Investor in the best interests of our community. If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.

Politics : Formerly About Advanced Micro Devices

Public Reply Prvt Reply Mark as Last Read File

Previous 10 Next 10 Previous Next

To: Scumbria who wrote (41570)	11/17/1998 11:46:00 PM
From: Steve Porter	Read Replies (4) of 1572561

Scumbria, Unless anyone really cares about synthetic benchmarks which fit in the L1. I care about those and I'll tell you why: I can write code that fits inside a normal (64K) L1 cache and data that fits in there too.. therefore, with the advent of instructions in 3d-now and soon KNI, I can preload the data into the cache, run compute intensive operations (matrix mults, etc.) at very high-speed. What the high DRAM latency really forces is for programmers to re-learn how to code. A lot of programmers today have no idea about tight code. I believe that anyone who is learning to code in school today should be forced at some point to spend an entire semister programming on a Commodore 64.. then they will learn about clock-counts and the like. Regards, Steve

Report TOU Violation

Share This Post

Public Reply Prvt Reply Mark as Last Read File

Previous 10 Next 10 Previous Next