Intel Investors - Intel's ISSCC Katmai Paper & HP's PA-RISC 8500 abstracts are listed below.
A second Intel abstract on an 18 Megabit SRAM is also listed, with details about cell size, etc. for a 0.18 micron process.
Two abstracts for AMD's K7 are also listed.
Paul
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A 600MHz IA-32 Microprocessor with Enhanced Data Streaming for Graphics and Video
R. Senthinathan, S. Fischer, H. Rangchi, H. Yazdanmehr
Intel Corp., Folsom, CA
A next-generation P6 microprocessor adds 67 instructions for data streaming. Circuit enhancements include multi-grid C4 power distribution, decoupling techniques, improvements in dynamic circuits, and process voltage and temperature-compensated I/O buffer designs. The processor in 0.25µm 5-layer-metal CMOS achieves 600MHz.
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An 18Mb, 12.3GB/s CMOS Pipeline-Burst Cache SRAM with 1.54Gb/s/pin.
C. Zhao, U. Bhattacharya, M. Denham, J. Kolousek, Y. Lu, Y.-G. Ng, N. Nintunze, K. Sarkez, H.Varadarajan1
Portland Technology Development, Intel Corp., Hillsboro, OR
1MPG, Intel Corp., Hillsboro, OR
An 18Mb CMOS pipeline-burst cache SRAM achieves 12.3GB/s data transfer with 1.54Gb/s/pin I/Os using a source-synchronous I/O interface, reduced-swing output buffer, and high-bandwidth input buffer. The 14.3µm2 chip uses a 5.6µm2 6-T cell in a 0.18µm 6-metal-layer technology.
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A 500MHz 64b RISC CPU with 1.5MB On-Chip Cache
P. Barnes
Hewlett-Packard Co., Fort Collins, CO
A 64b PA-RISC microprocessor is migrated to 0.25µm CMOS and integrated with on-chip 1.0MB L1 data and 0.5MB L1 instruction caches. The 500MHz processor incorporates 140M FETs on a 21.3x22mm2 die and delivers >25 SPECint95 and >40 SPECfp95 at 360MHz.
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A 7th-Generation x86 Microprocessor
V. Andrade, R. Burd, G. Constant, J. Correll, M. Crowley, M. Golden, S. Hesley, N. Hopkins, S. Johnson, R. Khondker, D. Meyer, J. Moench, H. Partovi, R. Posey, F. Weber, J. Yong
Advanced Micro Devices, Austin, TX
A 7th generation x86 microprocessor fetches,decodes, and retires three x86 instructions per cycle in a 15-stage pipeline. The chip uses 0.25µm six-layer metal CMOS plus tungsten local interconnect.
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An Out-of-Order Three-Way Superscalar Multimedia h5 Floating-Point Unit
M. Golden, N. Juffa, S. Meier, S. Oberman, H. Partovi, A. Scherer,
F. Weber
Advanced Micro Devices, Sunnyvale, CA
An x87-compatible out-of-order superscalar floating-point unit in 0.25µm six-layer-metal CMOS executes traditional floating-point instructions at two FLOPS per cycle peak rate, 3DNow! SIMD
instructions at four FLOPS per cycle peak rate, and up to three MMX SIMD instructions per cycle. |
