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Technology Stocks : CYRIX / NSM

NSM 18.27

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Jul 31 5:00 PM EST

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To: Craig Freeman who wrote (30319)	11/20/1998 3:14:00 AM
From: Scumbria	Read Replies (1) of 33344

Craig, 1MB of L2 cache is about the all you see on Socket 7 mobos. Why? When you go above 1MB, the performance improvement (in single processor systems) tails off very quickly. Caches are only effective for reuse of code and data. The first time a code or data block is loaded, it will miss in the cache. Similarly, context switches incur a large percentage of cache misses. Even with an infinite sized cache, a certain fixed percentage of memory accesses would miss in the cache. As clock speeds increase to 1GHz and above, high performance systems will have to use more sophisticated solutions than traditional sdram or rdram. There are other types memories available, i.e. edram, sram, etc. which computer architects will have to take advantage of. Scumbria

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