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Technology Stocks : CYRIX / NSM

NSM 18.27

0.0%

Jul 31 5:00 PM EST

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To: Steve Porter who wrote (30335)	11/20/1998 4:14:00 PM
From: Scumbria	Read Replies (1) of 33344

Steve, So you optimize the design, or create a little scratch area, that is separate of the cache that has the ram address and range scribbled into it on a cache load.. The scratch area would be very large and would consume a lot of power. It would also load down the cache address bus, which would seriously impact clock rate. Hopefully I'm giving you some feel for the types of implementation problems that CPU designers face. The L1 cache is invariably the worst speedpath in a CPU design. It is almost impossible to add any functionality to it without decreasing the clock rate. Scumbria

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