Tom, SI-Shark, and other techies:
I've posted below a portion of a press release copied from Yahoo. I would like to use it to re-open the discussion of GaAs vs silicon. If I remember correctly, last fall SI-Shark expounded at great length on this board about the various types of chips and suggested that CMOS and Bi-CMOS (?) or some other form of Silicon (I'm a horticulturist and this is all Greek to me) would eventually replace GaAs in all applications. I copied a few of those posts and showed them to a brilliant EE professor friend of mine hoping that he could resolve the issue for me. Unfortunately he gave a very non-commital response--"well maybe it could be this but then again maybe that, it all depends on manufacturing technology,blah,blah,blah...good luck with your investments." When I bought VTSS last summer I thought this was the future direction for all chips. Now it seems this may be a temporary technology. As soon as I can find it again, I'll also post a release from Qlogic which discusses a new fast CMOS based chip. Any help you insiders can give in sorting all this out and also perhaps re-stating the following press release in more layman level terms will be greatly appreciated.
Thanks,
Bob
********************************************************************* Monday January 13 8:17 AM EDT
Vitesse extends high-performance ASIC line with
low-power Standard Cell Family
CAMARILLO, Calif.--(BUSINESS WIRE)--Jan. 13, 1997-- Vitesse Semiconductor Corp
Monday announced the SLX Standard Cell ASIC Family.
Featuring a dramatic increase in performance and flexibility, this new array family builds upon
Vitesse's successful GLX Gate Array Family, introduced in 1995.
``Vitesse's new release pushes the high-performance envelope, offering both reduced power and
enhanced speeds up to 5 GHz,'' said Jim Gramacki, director of semicustom products at Vitesse.
As in the GLX family, SLX macrocells are available in either full-speed ( 7/80.13 mW/gate) or
half-power ( 7/80.07 mW/gate) versions. GaAs Power Management is used to further reduce
power by powering down portions of the circuit, depending on the mode of operation.
``This is an important innovation because Vitesse ASICs are virtually frequency independent (unlike
CMOS and BiCMOS, whose power consumption increases with the clock frequency), and GaAs
Power Management provides a means to further reduce power for low performance or seldom used
portions of a high-performance design,'' Gramacki said.
``SLX has extended the speed boundaries, adding hard-to-beat flexibility to the low-power,
high-integration foundation of GLX,'' he continued. ``In addition, SLX combines the cost benefits of
a high-yielding process, reduced die sizes and low-cost, thermally enhanced plastic packaging to
produce a semicustom product family that falls below the CMOS price-performance curve.''
SLX products use Vitesse's production-proven 0.4 micron L H-GaAs IV, four-layer metal process
to implement Standard Cell arrays with a well-characterized library of communications and
ATE/instrumentation megacells.
Embedded megacell blocks can be incorporated into any of the SLX base arrays to facilitate
system-level design. Compiled SRAM blocks of up to 64k bits, multiport register files, PLL
(phase-locked loops) and timing verniers are available now. Other megacells are currently in
development.
SLX arrays have room for 15,000 to 220,000 raw gates, with a utilization factor ranging from 60
percent to 70 percent. The SLX15K will support up to 87 signal I/O and is available in a 128
PQFP. The SLX40K offers up to 103 I/O and is packaged in a 160 PQFP.
Available in a 208 PQFP, the SLX100K will support up to 135 signal I/O. The SLX120K offers up
to 151 signal I/O and is packaged in a 240 PQFP. The SLX220K has up to 187 signal I/O and is
offered in a 340 PQFP. All I/O are configurable to industry-standard TTL, LVTTL, ECL,
LVPECL, CML, LVDS, GTL or HSTL.
SLX makes it possible to design critical system blocks with aggressive speed and power
requirements. Applications include switching networks, serial links, very high speed data bus
transfers, DSP functions and critical timing blocks.
SLX arrays are supported by Vitesse's GaAs Logic Design Environment (GLIDE), which is
supplied with design kits to supplement popular EDA design platforms such as Cadence, Mentor,
Graphics, Synopsis and Viewlogic.
Designs for all members of the SLX family are being accepted now with prototypes and production
volumes immediately available. SLX arrays sell for less than 1/10 cent per used gate in volume, with
NRE fees starting at about $30,000. .....
...snip...
**********************************************************************
Tuesday January 7 8:23 PM EDT
QLogic saves design costs and real estate with the
industry's first fully integrated single-chip Fibre Channel
controller
COSTA MESA, Calif.--(BUSINESS WIRE)--Oct. 28, 1996--
Backward-Compatible to Parallel SCSI Allowing
Cost-Effective Migration
Securing its technological leadership position, QLogic (NASDAQ:QLGC) on Monday announced it
will begin sampling its ISP2100 PCI-to-Fibre Channel controller to OEM customers.
Supporting all Fibre Channel classes of service, the ISP2100 is optimized for high-bandwidth SCSI
storage applications, and is the first Fibre Channel adapter chip to support integrated one
gigabit-per-second transceivers, substantially reducing cost and real estate requirements.
Integrated Transceivers
The integrated one gigabit-per-second Fibre Channel transceivers of the ISP2100 enable direct
connection to copper-based cabling. In the past, such transceivers have only been available from
suppliers utilizing expensive gallium arsenide (GaAs) process technology. QLogic's ISP2100 is the
first product to support integrated full-speed transceivers in a conventional CMOS-based process,
significantly reducing the overall solution cost. Fiber optic cabling can also be supported.
Backward SCSI Compatibility
Also of great significance to industry OEMs, many of which are QLogic customers, the controller is
virtually code-compatible with QLogic's industry-leading ISP1020 and ISP1040 PCI-to-Parallel
SCSI host adapter chips, so that a common software driver can accommodate both devices.
"Use of the ISP2100 in tandem with QLogic's ISP1020/1040 enables applications to transparently
support either parallel SCSI or Fibre Channel," said Larry Fortmuller, vice president and general
manager of QLogic's Computer Systems Group.
"This lets existing parallel SCSI customers retain their host software and training investments while
migrating to new Fibre Channel-based designs. This kind of host software compatibility is
unprecedented in the industry, and is unique to QLogic."
The Technology
The ISP2100 single chip PCI-to-Fibre Channel solution supports a 264-megabytes-per-second,
64-bit PCI host interface, a RISC processor which manages the data flow between the host system
and Fibre Channel interface, and a one gigabit-per-second Fibre Channel Engine (FCE).
Fibre Channel is a one gigabit-per-second data transfer interface technology that maps several
common transport protocols including IP and SCSI, allowing it to merge high-speed I/O
(input/output) and networking functionality in a single connectivity technology. Fibre Channel is an
open standard as defined by ANSI and OSI standards and operates over copper and fiber optic
cabling at distances of up to 10 kilometers.
It is unique in its support of multiple interoperable topologies including point-to-point,
arbitrated-loop and switching, and it offers several qualities of service for network optimization. With
its large packet sizes, Fibre Channel is ideal for storage, video, graphic and mass data transfer
applications.
Pricing and Availability
The ISP2100 samples will begin shipping in December, with production beginning the first quarter of
1997. Pricing for the ISP2100 starts at $150 for sample quantities.
........snip.........
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