MB,
What will this mean for the chip equipment makers?
12:41pm EST 19-Nov-98 Goldman Sachs (MOORE) INTC INTC.O
Intel Corp. : Breakfast w/CFO Andy Bryant; RL
Goldman, Sachs & Co. Investment Research
Intel Corp.
* * Breakfast w/CFO Andy Bryant; RL * *
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* This morning we had breakfast with Intel CFO Andy Bryant. Mr. Bryant explained and elaborated details of several key issues from the analyst meeting last week, including further detail on the cost
cutting efforts. The overall tone of the meeting was positive, consistent with the events of recent weeks (the positive preannouncement and the analyst meeting).
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Joe Moore (New York) 1-212 902-6834 - NY Equity Research
========== NOTE 12:33 PM November 19, 1998 ===================
This morning, we met with Intel CEO Andy Bryant on his investor relations tour on the East Coast. Last week's positive preannouncement and subsequent analyst meeting took some of the drama away, but we heard substantial positive, informative details on some of the topics touched on at the analyst meeting. We list a few of the important bits of information below:
* Reiterated that business strength is widespread, across all
microprocessor categories but also across flash, networking, chipsets, graphics, etc. As the company said at the analyst meeting, Intel's inventories are likely to be at an even lower level at the end of Q4 than at the end of Q3, as they remain sold out. The company has combed the customer base for excess 'safety stock inventory', and while they said that some customers would like to do that they are
currently unable to. The company will not be able to respond to any surge turns bookings demand in December. They increased production input in July and then again in September, so significant supply
should still come online by the end of Q4. Mr. Bryant reiterated that they have plenty of capacity and it is an issue of wafer starts.
* There is still a debate within Intel about the impact of Y2k on the
seasonal trend through 1999, and the company feels that there is adequate rationale for almost any argument that you could make. As a result, the strategy is to have enough capacity and inventory buffer
to handle any spike in demand that they might see in 99. Still too early to make any real comment on Q1, which will require sell through data.
* The cost-cutting effort is surprisingly independent of fab loading, as the materials cost has driven a substantially more variable-cost oriented model. The socketed Celeron (P2 w/integrated L2 cache in a
370 pin socket format instead of slot One) will clearly drive down variable costs significantly. That product ships in January, and there is clearly infrastructure being built for that now as we saw several 370 pin socket motherboards on display at Comdex. The company reiterated that while they had saved over $1 billion in Cap Ex from the reuse strategy in the 0.25 micron transition, the savings could be
greater in the 0.18 micron transition since there will be no greenfield fabs in 1999 (as 0.25 micron fabs are transitioned to 0.18). Overhead cost per wafer on 0.18 micron should be substantially lower in the early ramp than the cost was on a 0.25 micron wafer at the same point in the 856 ramp.
* The company still has not finalized the budget for 1999 (and it could be up, down, or flat from 98 levels), minimizing capital spending is clearly a major part of the plan. |
