Re: chiptech.com
"The K7 will debut at 600MHz. How can they ensure this? K7 is superpipelined, as the incredibly overused term goes. It is specifically designed to run at higher clock speeds than the earlier K6 core, which is quite aged by now and may have difficulty breaking much beyond 500MHz (at least, until it shrinks to 0.18um). This first K7 will have 128KB of L1 cache. At the time, the WinChip-3 will have 128K L1, and the K6-3, Katmai, and Jedi will share 64K L1. The debut K7 will also sport 512K of L2 cache. Unlike in the Pentium II, the L2 cache will initially run at a third the speed of the processor. Apparently, AMD is unconvinced that 300MHz cache memory will be reliable enough at that time, so they are opting for cache that effectively runs at the motherboard speed, seemingly confident that the huge L1 cache will be enough to offset this potential bottleneck. The bus speed, as widely touted, runs at 200MHz bus and is a rather instrumental feature in bringing interest towards the K7. Interestingly enough, the 200MHz bus should be able to run with conventional PC100 SDRAM, as it utilizes two alternate banks of 100MHz ran to effectively run the bus at that higher speed."
Was I right, or was I right?
exchange2000.com
Kevin |
