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Politics : Formerly About Advanced Micro Devices
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To: Kevin K. Spurway who wrote (42579)12/2/1998 2:53:00 PM
From: Paul Engel  Read Replies (2) of 1584985
 
Kevin - Re: " it may be that Intel will have a harder time getting
to .18u."

As a matter of fact, inside Intel's "Museum" in Santa Clara, there is a host of engineers already singled out for Personal Achievement Awards for specific development areas of the 0.18 micron process.

These awards have evidently been granted months ago with requisite time for picture taking, award presentation, and display construction for the Intel Museum.

A reasonable conclusion is that Intel's 0.18 micron process development is essentially complete with current activity focused on yield improvement.

In fact, at the Intel Analyst meeting last month - one day after the AMD analyst meeting - Sun Lin Chou - Intel's VP of Technology Development - presented a "foil" displaying the defect density of the 0.18 micron process vs. time along with the older 0.35 and 0.25 micron processes when they were being developed and ramping into production.

The 0.18 micron process defect density - according to that graph - is nearly equivalent to the 0.25 micron process defect density when it went into production. Needless to say, the defect density curves for both continue to decline over time. In fact, Sun Lin's point that he tried to make was that the slope of the curve - Defect Density vs. time - was steeper (falling faster) for the 0.18 micron process than the 0.25 or 0.35 micron processes.

For your reference, Intel is presenting a paper at next year's ISSCC on a 0.18 micron 16 MegaBit SRAM - which indicates that is the "test chip" that Intel is using for their 0.18 micron process development, debug and defect reduction studies.

Paul
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