Design reuse rules at TI's ASIC
operation
By David Lammers
EE Times
(12/03/98, 1:48 p.m. EDT)
DSPs may be king at Texas Instruments Inc., but they share the crown with
the company's ASIC division, where design-for-reuse has been the ruling
principle for several years.
A Web-based intellectual-property repository has been in operation since
February and is accessible to TI ASIC designers worldwide. Called the
Dream (design reuse and methodology) system, the repository now includes
about 100 IP cores. Most of the intellectual property, including DSP cores,
comes from within TI's product groups. Once the system managers at TI are
satisfied that all security issues have been resolved, Dream will be made
accessible to select external customers.
To bring in both internal and third-party intellectual property, the company
has set up a structured approach to ensure that IP quality meets definable
standards.
"Right now and over the next year or two, the focus is to build a set of IP
that adheres to a high standard of quality," said Richard Kerslake, worldwide
system-level integration marketing manager at the company. "Second, we
want to enhance our methodology so we can easily integrate IP, in what we
call TI's Fast and Easy design environment."
In 1990, TI undertook a concerted effort to optimize its next-generation
process technology to an ASIC backplane. The problem at the time,
Kerslake recalled, was that "every business unit tuned its process to its own
needs, and we couldn't port its cores" to ASIC designs.
Because HDL, synthesis and RTL-based design techniques were being used
within the ASIC division to meet time-to-market requirements, TI made a
decision to "get everyone on the backplane," i.e., the same essential process
technology and design methodology. A company-wide approach to module
creation, dubbed Time Builder, is the third leg of the approach.
"TI has a ton of IP within the company," said Scott Eisenhart, ASIC product
architecture manager. "The challenge was to get to a point where we could
use it, leverage it, harmonize it, readily integrate it."
The first effort involved the development of coding guidelines. A group
developing an analog block must meet certain design standards so that the
analog core can be matched with other cores being developed in parallel by
other design groups. Engineering managers "must execute to a set of
deliverables," the quid pro quo being that the design team will be able to use
other cores that will shorten its own time-to-market on later projects.
"Our engineering management has asked us to rate IP to gold, silver and
trash levels of quality, and we are in the midst of developing an internal 'J.D.
Power' kind of review of cores," said Eisenhart.
One challenge has been to take the burden of support off the product
managers. If a group is developing a standard product that needs to be
included in the IP repository, the already harried product managers can turn
to Dave Shoemaker and his group, informally called the IP rescue squad.
The team of about a dozen engineers will work to ensure that a core meets
TI's reuse quality standards and will help maintain the core through its
lifetime within the Dream repository.
"There is a real fear of the support burden," Eisenhart said. "The refrain of
the engineering manager is that his resources will get suckered in to
supporting a core," masking the initial goal of completing a standard product
core.
Eisenhart said TI takes "a pragmatic approach" to external IP. Besides
ARM, TI was one of the early customers of 3Soft, and the company has "a
healthy budget" allotted to buying third-party IP in 1999.
The company has a central EDA evaluation and purchasing group, and a
member of that group, Ann Phillips, was assigned the task of evaluating
third-party IP vendors. "Ann went off and surveyed the entire third-party IP
marketplace," Eisenhart said. "What she concluded is that there were 17
viable IP providers, and we now have active engagements with six. We
purchased IP from all of them and developed a standard template for how
that IP would fit in, even though each IP core was unique."
Besides the ARM cores, the arsenal of third-party IP includes several PCI
cores, high-level data link controllers, 8052 processors and other modules.
The "vast majority" of IP that makes up the 100 or so cores in the Dream
repository come from within TI, Eisenhart said. "One aspect of IP is that you
need access to the developer. If you push the technology envelope on a
particular core and you ask to talk to the developer, in some cases the key
developer may have left. If we go to a design team within TI, the entire
product organization has knowledge of that IP."
Asked Kerslake, "Do I think we are going to license 20 ARMs every year?
Of course not. But again, the goal is to be 'Fast and Easy,' and we remain
pragmatic. There are not 20 vendors out there that really know how to play
the game [of providing external IP]. But we do work with Mentor Graphics
and with Sican, a German-based IP vendor, and there will be others."
Kerslake, who recently relocated from the United Kingdom to Dallas,
believes "there is an aspect of the IP industry which can be described by
saying that many of the companies think they will become the next ARM or
MIPS, and they apprise us of their business models to that regard. There is a
worrisome minority which has IP that does not back up its claims . . .
Overall, our experience has been positive. But the industry in general is
immensely immature." |
