December 07, 1998, Issue: 1038
Section: News
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Scheme calls for radical changes to consolidate packaging, assembly and test -- Startup aims to put new spring in wafer test
Brian Fuller
Tokyo - A low-profile probe-card company last week unveiled a new process it claims will consolidate entrenched, time-consuming test and packaging methods, slash costs and bring Moore's Law-type scaling to the back end of semiconductor manufacturing.
FormFactor Inc. (Livermore, Calif.), a closely held startup already involved in wa-fer probe, detailed its Wafer on Wafer (Wow) technology, designed to allow the traditionally separate steps of packaging, assembly and test to be consolidated at the wafer level.
The technique uses so-called Microsprings attached to the wafer for various forms of test and burn-in-before dicing-and ultimately for attachment to a printed-circuit board, according to Jim Healy, vice president of corporate marketing, and a long-time semiconductor equipment hand. The result could be much better control of yield problems on the back end.
The company is targeting memory parts that are cost-sensitive and approaching high volumes, where the efficiencies and cost-savings of the Wow technique can be realized.
Healy does acknowledge challenges ahead in consolidating back-end methodologies, which traditionally are run by different groups. "We're talking about changing an industry, changing an infrastructure. We understand that."
The FormFactor technology is at least a year away in its ideal form, but the company is laying the groundwork to ride the coattails of Rambus DRAMs. In their complexity and expense, those parts are requiring a retooling of test and assembly techniques.
What the company and its founder, Russian emigre Igor Khandros, hope to do is push all test-from pre-burn-in to burn-in to low-speed and high-speed test-to the wafer level. Wafer test is not new, but this technique notably shifts singulation, or dicing, of the wafer from an early step to nearly the last step in the process, eliminating costly steps and extra test handlers and allowing engineers a quicker look into design and fabrication errors, Healy said.
The first step of the process employs a modified bonder to attach tens of thousands of Microspring contacts to the wafer, as are already used in other FormFactor probe products. The springs, made of gold for its electrical characteristics, are plated with nickel alloy to give them spring action. A trace is re-routed from the traditional bonding pad to the springs, which are arrayed on the wafer.
Users can then customize their test methodology, for example starting with wafer-level burn-in and long-cycle test, and then move to a redundancy/repair cycle and so on. After test, the wafer is diced and the contacts are either socketed or soldered to a substrate. The company claims the approach is better than solder balls because it can handle a finer pitch and better than wire bonding because it can maximize pin count. Once placed on the board, the dice can be capped with a heat sink and encased in plastic as well.
The approach allows the IC manufacturer to follows Moore's Law on the back end, which is under threat since test time increases linearly with the number of DRAM bits. Dataquest has reported that the cost model for a 16-Mbit DRAM is $1 per good device on the back end, but vendors are spending nearly five times that on 64-Mbit parts. With Direct Rambus parts ramping, demanding new packaging and expensive test solutions for high-speed performance, Healy and Khandros estimate that back-end costs for the parts could rise by more than 50 percent.
"You never know where the land mines are in something like that but from everything we can gather, it's for real," said Fred Zieber, a market analyst at Pathfinder Research (San Jose, Calif.). "Clearly there's a chicken-and-egg problem in getting it going. You have to have people doing it and people to accept it. It's not an easy deal at all."
Indeed, FormFactor executives don't pooh-pooh the issues of acceptance. While a half-billion dollars in potential revenue has been bandied about as a possible target in a few years, Healy, former president of tester vendor Credence, said he recognizes the entrenched nature of the back-end process. He said that during one customer meeting involving the separate assembly, package and test teams, members from each team, unfamiliar with each other, exchanged business cards and introduced themselves.
Speedy test
Market analyst Dan Hutcheson of VLSI Research Inc. (San Jose) said the Wow approach represents a holy grail in test methodology. "Where this gets interesting for users is to allow them to move speed testing up to probe," he said.
Rather than wait weeks from the beginning of the back-end process until speed test kicks in, the FormFactor process would push it up to days. In that way, a company would avoid sand traps in which thousands of wafer starts, worth say $15 million to $20 million a week, get pushed down the line and engineers don't find out for weeks that they've got 20 to 30 percent yield loss or speed drop, Hutcheson said.
"You can turn yield excursions from weeks to days, you do more cycles of learning in a given production run," he said. "Ideally, you'll get to entitled yields faster. That's not what packaging offers."
Reliability and market acceptance are clearly key to getting the technology off the ground. FormFactor has made one step in the credibility direction by licensing the Wow technology to Shinko Electric Industries Co. Ltd. (Nagano, Japan), a company affiliated with Fujitsu.
"We licensed the Wow technology with the expectation that it will simplify test processes. The more a device becomes high-density and high-speed, the more the test process becomes complicated," said a spokesman of the Japanese company.
Glenn Farris, product manager for high-speed memory test at ATE and memory-test vendor Teradyne (Boston), said there are a host of open issues to be sorted out before Wow can turn heads.
"There are technical issues," he said, "such as can you get all those springs on a wafer and make it work? Then there's the economic factor. In the end, is the overall cost less expensive than traditional packaging and testing?" FormFactor also needs to provide the high-bandwidth interfacing capabilities necessary, for instance, to accommodate a tester like Teradyne's big-iron Aries tester, Farris said. Teradyne is talking with FormFactor and monitoring the process development, he added.
Gary Fleeman, memory product manager at Advantest America (Santa Clara, Calif.), said, "The real benefit of Wow is in reducing the number of times a device is handled, or insertions. Many major companies are desperately trying to cut insertions.
"However," he added, "it's difficult to build a test system that can handle 1,200 die, the number mentioned in FormFactor's Semicon paper. Even so, we still will need multiple inserts because at-speed testing is dramatically different from long-cycle burn-in testing. And a lot of memory suppliers already do a lot of ac speed work on the wafer, although not 128 devices in parallel."
Chip to wafer scale
At the packaging level, many other companies are working on techniques to attach packages while chips are still in wafer form. This heavy development activity has taken off in the past couple of years with the advent of chip-scale packaging (CSP), which adds so little to the IC that it becomes feasible to add packages to a single wafer instead of to many separated chips.
"Wafer scale is a natural extension of chip-scale packaging," said Thomas Di Stefano, a founder of Tessera (San Jose, Calif.), which has licensed its CSP technology to many companies. "One thing that gives it impetus is that wiring normally done on the substrate, like power and ground, can be put in the package, which can reduce the number of I/Os a chip needs."
But the challenges to get wafer-level packaging into production are still high. Tessera has been working on its technique for almost six years, and it's only now shipping parts to IC houses.
FormFactor, as of midyear, had been capitalized to the tune of $13.5 million with backing from Institutional Venture Partners, Mohr Davidow Ventures, Morgan Stanley Venture Partners and Leeway & Co. William Davidow is chairman and the company lists on its advisory board TI's Jack Kilby, Mentor Graphics CEO Wally Rhines, former Intel and now-Dell executive Carl Everett, among others.
It hopes to sell the industry on a Rambus-like business model in which it licenses the technology and process to other companies, such as Shinko. If those companies find compelling cost-savings, and margin advantages for their customers, the process could take off, observers said.
"There's going to be a fair amount of doubt until you get to volume and until reliability gets established," said Pathfinder's Zieber.
But some don't see the process taking hold in the mainstream."I don't think we're going to see chip-scale packaging for three years or so," said Adrian Proctor, general manager of memory-module maker Dane-Elec Corp. (Irvine, Calif.). -Stan Runyon, Terry Costlow and Yoshiko Hara contributed to this report.
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