IBM samples 256-Mbit parts, joins 10 firms in endorsing format -- DDR picks up steam as next-gen DRAM choice
David Lammers
12/07/98
Electronic Engineering Times
Page 20
Copyright 1998 CMP Publications Inc.
Santa Clara, Calif. - IBM's Microelectronics Division has started sampling a 256-Mbit double data rate (DDR) synchronous DRAM that will go into volume production in mid-1999 at its fabrication facility in Essonnes, France. IBM also said it will put its muscle behind DDR II, a collaborative effort to develop a memory architecture that will deliver 3.2-Gbyte/second throughput for servers and 9.6-Gbyte/s throughput for point-to-point connections in small systems. DDR II is scheduled to be ready for introduction in 2001.
IBM was among 11 DRAM vendors and large computer manufacturers to voice their collective support for the DDR specification last week, putting the DDR SDRAM back in the race for memory slots alongside the Direct Rambus DRAM (D-RDRAM). After a series of delays, the specifications for the DDR components and 200-pin DDR modules were agreed on this autumn. Only minor issues remain to be resolved for dual-in-line memory modules.
In an important development, companies participating in the Joint Electronic Device Engineering Council (Jedec) committee are buckling down to the task of getting DDR II ready for introduction by 2001. DDR I devices in 64-Mbit densities, which are coming on the market now, and in 256-Mbit densities, which will arrive late next year, operate at 133 MHz at 2.5-V operation. By reading data from the rising and falling edges of the clock, a maximum performance of 266 Mbits/s per pin can be achieved, IBM reported. By improving the electrical interface and moving the frequency to the 266-MHz range, a throughput of 400 Mbits/s per pin is feasible with DDR II.
Steve Przybylski, principal analyst at the Verdande Group, said the work on DDR II "gives the DDR initiative much more credibility, ensuring the server and networking people that this is not just a temporary and partial solution to their memory needs. If you really push the DDR technology," he said, "you can reach the same 1.6-Gbyte/s peak bandwidth performance [as D-RDRAMs], but normally DDR won't be as fast as the Direct Rambus parts on bandwidth."
Though microprocessor vendors Intel, Advanced Micro Devices and Cyrix have endorsed the Rambus architecture for PCs, as has Compaq Computer's server division, Rambus has yet to convince most server manufacturers that the narrow, 16-bit Rambus channel can effectively scale to the multi-gigabyte main memories used in larger servers, analysts said.
Cost is also important, and the DDR components and modules may be less expensive than Rambus memories and modules. All of the additional costs incurred by the Rambus license fee, the requirement for chip-scale packaging and the need for high-speed testers, are multiplied when a high number of the memories are used per system.
Przybylski said server manufacturers typically use a 64-bit memory bus with memory controllers that can control more bits per pin, and in this way can support very large memory configurations. By using switches to control a large number of modules, large system vendors may feel more comfortable with the DDR memories, rather than the "rigidly specified physical configuration used in the Rambus approach," he said.
But once Rambus memories go into volume production, the sheer volumes that may be achieved in the PC sector-which accounts for 60 to 70 percent of all memory bits shipped-could make it difficult for the DDR parts to maintain any cost advantage next year, Przybylski said.
Samples shown
Fujitsu Ltd., Hitachi Ltd. and Mitsubishi Electric Corp. unveiled 64-Mbit DDR DRAMs in October (see Oct. 12, page 37). Last week, NEC Corp. said it was ready to begin sampling a 128-Mbit SDRAM with a CAS latency of 2.5 ns built in a 0.22-micron process.
Bob Merritt, a research analyst at Semico Research (Phoenix), said the support of 11 DRAM and system makers for DDR "is a very significant announce- ment because of what it says, as well as what is not being said. It says that system and PC designers are now assured that one branch of the DRAM family will follow the traditional path of previous high-volume DRAMs. The Jedec vote back at the 64-k DRAM generation established that DRAM manufacturers would focus on lowering component costs by maintaining design simplicity and evolutionary architectural changes. This announcement confirms that adequate support will continue."
Merritt added that "many companies are still concerned about the remaining technical issues and cost forecasts related to the Direct Rambus DRAM architecture." The critical comparison, he said, is not cost per se but "the cost/performance of one DRAM architecture vs. another. This total cost includes the chip set, the connectors, the completed memory module and the support infrastructure. The announcement means that PC manufacturers can directly compare the product availability, cost and performance of more than one architecture, and then select whichever is the most competitive at any given time."
Risk moderated
Lane Mason, a strategist at IBM's memory division, said "because servers use tremendous amounts of memory, any little incremental cost is magnified. Also, the server people are attracted to DDR because of the relative lack of risk in the technology. It leverages the same kind of connectors and modules and packaging that they are used to, so DDR minimizes the technical risk for designs coming to market in 2001 and 2002."
IBM will make a limited number of 64-Mbit DDR SDRAMs, and only for development projects, Mason said. The real thrust will take place with the 0.2-micron 256-Mbit chip that will run at 133 MHz. IBM sent samples of that part to a large external OEM in November. In the future, IBM will apply a 0.175-micron process, and Mason said a 512-Mbit DDR SDRAM "is on our road map." A 128-Mbit version will emerge in late 1999.
Vijay Lund, director of advanced server engineering at IBM, in a statement touted DRR's "reliability features-such as improved error correction-that allow us to build systems with high availability. The efforts of Jedec to define a common DDR specification gives us confidence that we will be able to accommodate future system requirements in performance and capacity in a cost-efficient manner."
Graphics board manufacturers are also likely to adopt the DDR memories, said Victor de Dios, a DRAM market analyst based in Neward, Calif., in part because of DDR's excellent latency and acceptable bandwidth. Many graphics manufacturers compete on price, de Dios said, and some of them will not spend on a Rambus license.
DDR DRAMs could achieve 12 to 17 percent of the total DRAM market by 2001, with as much as half of them going into graphics subsystems and the rest into servers, de Dios said. By late 1999, most higher-density SDRAMs will offer DDR capability as a bonding option, he said.
"Rambus will penetrate at the lower ends of the market," de Dios said. "But for the four-way and eight-way servers, with multiple buses, the timing specifications on the Rambus approach are so tight that it is difficult to design with the Rambus channel."
For the server market, Intel expects that its customers will use both RDRAMs and SDRAMs. AMD recently said that its K7 processor and supporting chip sets will support either synchronous DRAMs or the Direct Rambus memories.
December 07, 1998
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