Japanese chip makers spin first DDR DRAMs
Anthony Cataldo
10/12/98
Electronic Engineering Times
Page 37
Copyright 1998 CMP Publications Inc.
Tokyo - As if awaiting the same cue, three of Japan's memory suppliers have just announced 64-Mbit double - data - rate DRAMs to add to the mix of high-speed DRAM types that will start to ramp up late this year.
Fujitsu Ltd., Hitachi Ltd. and Mitsubishi Electric are trying to push the new open-standard DRAM technology into a range of applications ranging from PCs to high-end workstations and servers, where the clock frequencies of CPUs have started to outstrip DRAM speeds. While many vendors expressed optimism that DDR will be adopted in high-end systems, questions remain as to whether they will make a good fit at the midrange to low end of the PC market.
DDR devices, which have been made into a Jedec standard, achieve high speeds by including DLL circuitry so that the device reads data on both the rising and falling clock edges of each clock cycle, effectively doubling the bandwidth. The concept is not unlike that used in Direct Rambus DRAMs, which will also soon start rolling out.
The fact that Direct Rambus is a protocol-based interface allows it to use a narrow 16-bit channel to achieve high speeds with a low pin count. DDR is a more con- ventional approach based on the low-voltage-swing 2.5-V Stub Series Terminated Logic-2 (SS-TL-2) interface for synchronous devices. Both claim to provide up to 1.6-Gbyte/ second peak bandwidth.
Because the DDR devices conform to a Jedec specification, they use a bidirectional strobe signal, a 2.5-V SSTL-2 interface and 66-pin, 400-mm thin small-outline packaging. New184-pin dual in-line memory modules are also required.
"This new technology is an open, non-proprietary evolution of standard SDRAM which doubles the peak bandwidth and is much easier to use for error correction than other advanced DRAM types," said Cecil Con-kle, assistant vice president of marketing at Mitsubishi Electronics America (Sunnyvale, Calif.). "That's why we expect DDR SDRAM to be used widely in high-end servers and workstations for scientific, financial, networking and communica- tions applications. Depending on how development efforts progress for related chip sets, these cost-effective advanced DRAMs may also be popular in high-performance PCs."
Along with needing the support of off-the-shelf chip sets, DDR devices will need new high-speed clock drivers and new Jedec-standard modules to be used in high-end PCs, Conkle said. Because of these infrastructure requirements, chip- set suppliers, motherboard makers and PC companies have been reluctant to adopt DDR for midrange to low-end PCs because of the additional costs they entail, said Misao Higuchi, manager of memory engineering of NEC Corp. For the middle to low end of the PC market, NEC is pushing its Virtual Channel Memory architecture, which has garnered support from three of Taiwan's chip-set manufacturers but still lacks widespread support from memory vendors.
While DDR DRAMs have so far failed to gather backing from chip-set suppliers-most notably Intel Corp., which has chosen Direct Rambus for future chip sets-a number of manufacturers have announced they will produce the memory devices and are optimistic that high-end system manufacturers will develop their own memory controllers with hooks to DDR.
Hitachi will soon offer DDR devices in by-4, by-8 and by-16 configurations, each having 83-, 100- , 125- and 133-MHz speed grades. Measured on a per-pin basis, data-transfer rates are 166, 200, 250 and 266 Mbits/s, respectively. They will have sequential and interleaved burst sequence options, with burst lengths of 2, 4 or 8 per pin. CAS latency options are 2 and 2.5.
Made on a 0.25-micron process, the DDR devices will be available from Hitachi in November in Japan. The company will make 10,000 of the DRAMs per month starting in January and will increase volume production to 800,000 units/month by the end of next year, according to a Hitachi spokesman. The price will be about $14, except for the 133-MHz parts, which will cost $22.
Fujitsu, meanwhile, will also start selling samples of 64-Mbit DDR chips with by-4, by-8 and by-16 I/O widths in November for about $14. Made on Fujitsu's 0.32-micron process, the devices will come in 83- and 100-MHz speeds.
Fujitsu will also sell 184-pin DIMM modules with DDR SDRAMs. Four configurations will be offered: 8M x 64 and 16M x 64 without ECC, and 8M x 72 and 16M x 72 for ECC types.
For its part, Mitsubishi is offering 64-Mbit SDRAMs in by-4, by-8 and by-16 configurations, with speeds as high as 133 MHz. There are three CAS latency options available: 1.5, 2 and 2.5, with burst lengths of 2, 4 and 8 for each data pin. Mitsubishi said its "-7.5" specification for the memory offers a first access time of 37 ns with a 133-MHz bus at CAS latency 2.5.
October 12, 1998
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