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Politics : Formerly About Advanced Micro Devices

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To: Elmer who wrote (43107)	12/9/1998 11:35:00 PM
From: Yousef	Read Replies (3) of 1571685

Elmer, Re: "Yousef, how about commenting on Intel's presentation at the 44th International Electron Devices Meeting on their .18u process. How does it stack up verses the competition?" Yes Elmer, I would be happy to comment on Intel's .18um process ... I will discuss a number of important improvements in technology. First ... Intel's device/FET technology. The .18um process has .13um printed gate NMOS FET's operating at 1.5V (for performance) and 1.3V (for low power). This means that the Leff for Intel's devices are at ~.08um. To achieve these short gate lengths, Intel has incorporated Optical Proximity Correction (OPC) and perhaps Phase Shift technology to be able to extend their 248nm laser scanners. This is so aggressive that no other company will produce shorter devices using 248nm lithography in manufacturing. This all results in very high drive currents (Idsat) of 940ua/um NFET and 420ua/um PFET while off-currents are kept well under control. These drive currents coupled with the reduced operating voltage will give much higher performance than their .25um process. Second ... Intel has continued to improve their shallow trench isolation technology. They have achieved a .56um N+/P+ spacing with a 5300A trench depth. Most companies are trying to head to shallower trenches, but obviously Intel has "mastered" the deeper trenches which allow tighter N+/P+ spacing. The reason that N+/P+ spacing is important is because this "drives" the SRAM cell size. The 5.6um^2 cell size will allow large caches to be placed directly on-chip. Third ... SiOF is used as the dielectric in the backend. This provides lower dielectric constant (k) by about 15% over standard SiO2. The result is lower capacitance which leads to lower power and higher performance. Also, Intel has been able to achieve their performance targets without resorting to Copper or more exotic Low k materials. This means a higher yielding process. Lastly ... Intel has demonstrated a 900mhz 16Mb SRAM in this process. This is more important than most realize because the .25um 4Mb process development test chip ran at ~ 400mhz. This means that there is probably more "Mhz headroom" above 900mhz ... And finally, this will be available in volume by mid-'99. No other CPU vendor will have a .18um process that will be able to touch the performance of this process. The process that AMD is purchasing from Motorolo will not meet this level of performance until 1+ year after the Intel release. Hope this helps. Make It So, Yousef

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