Dan, both Verilog, and VHDL are an attempt to generalize programmable logic. I have personally not used Verilog, but am familiar with VHDL. The rational for both is pretty much the same. Create a function level hardware language, that permits high level function librabies, and quick porting from one manufacturer's programmable logic to another, or indeed to an ASIC with minimal greef. The majic, is however a combination of the development platform, i.e. Synopsis, and Exlemplar, and the VHDL language. A simplified example of the development process running on one of these tools goes something like this.
1. You select the PLD manufacturer and device.
2. You get the VHDL library from the manufacturer in 1 above.
3. You create the logic function in VHDL targeted for the selected device
4. You compile the VHDL creating a netlist- description of the ckt.
5. You run the netlist into the manufacturer specific "fitter" for the device selected in 1 above.
6. You program the devices.
By changing the libraries in 2 and changing the fitter in 5 you can significantly ease the task of porting a PLD design from manufacturer to manufacturer, or even from technology to technology, e.g. PLD to ASIC The process is not, however, automatic and may entail significant messaging of the VHDL for the "new" device, but it is usually much easier than starting from scratch.
Hope this helps.
Mike |
