Hi Skeeter Bug; The statement, ... has typically grown in excess of the chip industry in general ... is true, but it is a backwards looking statement.
The biggest challenge to the programmable market is the ASIC market. ASICs use silicon a lot more efficiently than programmables, I think I mentioned that a $2600 Xilinx chip, which drops to $350 in volume, can be replaced by an ASIC that costs $25 in volume, and does much more, faster, etc., but is not reprogrammable.
So it all boils down to how useful it is to be reprogrammable. This is largely a question of how hard is to design ASICs that work right the first time. This is a design/simulation question, and is one that the chip tool industry is trying hard to solve.
My guess is that it will be solved, and this will brighten the future of ASICs over the next 5 years or so. (Of course this isn't going to help your puts much...)
Here's a typical EE-Times article that gives you an idea of where ASIC design tools are going:
Comet tool set's simulation speeds said to hit 150 million instructions/s -- Startup promises a 'Vast' coverification boost
That speed, said Hellestrand, lets software designers do real work before prototype hardware is available. "This is a new tool in the systems-engineering space that, for the first time, allows designers to build real hardware and software and run models very quickly," he said.
techweb.com
-- Carl
By the way, didn't XLNX and ALTR both have dropping $ sales over the last year?
P.S. That darned Xilinx schematic capture tool is starting to give me repetitive motion pains in my right hand. Just about every thing you might want to do with the Altera tool is more natural. Altera can be touch-typed, but with the Xilinx tool, I end up keeping one hand on the mouse, and the other hunts and pecks the keyboard.
In addition, their symbol editor is bizarre beyond belief. You can only move one pin at a time. About half the time when I try to save a symbol shape as the symbol for a different part (like when you are making a family of different size adders), it barfs and writes the symbol out to a nonsense named symbol file.
There are enough repetitive bugs that I can give hilarious demonstrations of them to the other engineers. I am really amazed that Xilinx is able to put up with it. If their silicon weren't so superior to Altera they would be in real trouble. |
