SI
SI
discoversearch

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor.  We ask that you disable ad blocking while on Silicon Investor in the best interests of our community.  If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.
Technology Stocks : Xilinx (XLNX)
XLNX 194.920.0%Feb 14 4:00 PM EST
 Public ReplyPrvt ReplyMark as Last ReadFilePrevious 10Next 10PreviousNext  
To: Bilow who wrote (2148)12/23/1998 4:59:00 PM
From: Lucinos  Read Replies (1) of 3291
 
If we had good design tools from the software houses, I always
thought ASIC could be a winner against reprogrammable chips
in every aspect until recently. About six months ago, we taped
out an ASIC design in 0.25um. The mask set cost over 150K.
The reticles took two weeks to build before we could have the
silicon started. The TAT for wafers were three weeks longer
than those processed in 0.35. However, those difficulties were
well expected and planned.

For this time, the 1st silicon was working and can be used.
However, we still took three more months of time and a quarter
million dollars (in reticles and wafers) to fix the design
for some minor problems (due to simulation and design tools)
and a minor spec change. Everything was finally working for us.
It was great, right? Not exactly. The wafer yield is a little
bit below our expectation at this moment, and the ESD is
still a little bit shaky... So, I would like to believe the
ASIC is no longer as simple as it used to be.

PL
Report TOU ViolationShare This Post
 Public ReplyPrvt ReplyMark as Last ReadFilePrevious 10Next 10PreviousNext  

HomeMailHotSubjectMarksPeopleMarksKeepersSettings
Terms Of UseContact UsCopyright/IP PolicyPrivacy PolicyAbout UsFAQAdvertise on SI
© 2025 Knight Sac Media.  Data provided by Twelve Data, Alpha Vantage, and CityFALCON News