Hi Walter Jacquemin; I found out why I was getting that stupid error, I think...
Most of the high end FPGAs use 4-input Look Up Tables (LUTs) to do their logic. Such an LUT can perform any possible function of four (boolean) variables. Naturally, good FPGA designers think in terms of functions of four variables, at least when creating the repetitive parts of their logic that use up the most space. I wanted to put a function of four variables into a LUT, (using the FMAP primitive to force it) but Xilinx (software) was convinvced it couldn't fit. The reason was that I described the logic using a 4 to 1 MUX, which has a total of 6 input pins (i.e. 4 data pins and 2 select pins). If you put six different signals into a 4 to 1 MUX, it wouldn't fit in a 4-input LUT, but if you use only four different (non-power) inputs, it will fit, just like any other function of four variables. This is a convenient way of describing the function, in my case, and really shows what is going on. (Note that Altera software easily maps such a use into a LUT.)
Finally I got it in using the "LUT4" primitive, which allows you to describe the logic in a LUT by a hex string of four characters. Needless to say, this is a little lacking in obviousness to the poor guy who has to modify it later, but it got around the problem. It also allows me to get rid of the FMAP primitives which are ugly anyway.
In addition, it turns out that using the LUT4 has allowed me to finally get the infamous "MULT_AND" gate to work. This is a primitive that was added to the Virtex line supposedly "exclusively for building fast and smaller multipliers.", but it is a hell of a useful little gate when you are trying to cram arithmetic stuff using the fast carry chains into a CLB.
Consequently, I can now fit a programmable IIR filter (single stage exponential, using a serial shift to determine the tap value as a power of two) into a CLB column at the rate of 2-bits per CLB, without having to use more than four (non-carry) outputs from each CLB. (There are eight non-carry outputs available on a CLB, but routing is a lot easier if you only use four of them.)
Xilinx has a sharp logical arithmetic guy who, I suppose, had that MULT_AND gate added, I'll edit his name into this note if I can find it. He is the reason that arithmetic is so much more efficient on Xilinx than Altera, given the same sort of process speeds.
Names are Peter Alfke, and Bernie New.
Okay you Xilinx software guys, how's about getting that mapper fixed to the point that I don't have to describe my logic with things like "7A86"?
-- Carl |
