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Politics : Formerly About Advanced Micro Devices

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To: Ali Chen who wrote (44065)	12/26/1998 9:15:00 PM
From: Elmer	Read Replies (1) of 1573092

Re: "for a modern superscalar superpipelined microprocessor, if the data delivery time (latency+bandwith) drops below certain limit (I would suspect the length of pipeline is the characteristic factor), furhther increase in L2 speed does not matter - there is enough stuff wating to be executed, and it shadows the processor's bubble due to L1 miss. Is this comprehendable for you?" Ali, let us grant that what you say is correct. The purpose of the Xeon is really to offer larger L2 than would be reasonable for a PII in a signle processor environment. The Xeon is aimed at a multiprocessor system where a faster and larger L2 will not only allow for slightly higher performance but more importantly, greatly reduced bus activity. This reduced bus activity allows for more processors to reside on the bus without saturating the bus. As a result, additional processors will allow nearly unity gain. This is the real reason for Xeons and this is why vendors are happy to pay much higher prices because the high system throughput justifies the higher cost of the Xeons. This is not a Winstone98 or Quake thing, but a TPC-C ideasinternational.com Notice the bottom table. That's the top 10 by price/performance. Every single one of the top 10 is a Intel Xeon system. The vendors aren't stupid Ali, they know value when they see it. EP

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