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Politics : Formerly About Advanced Micro Devices
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To: Bill Jackson who wrote (44197)12/28/1998 11:21:00 PM
From: Tenchusatsu  Read Replies (2) of 1572888
 
<With business and consumer tasks you can satisfy CPU demand for local cache 95% of the time with 128K, going to 256K takes you up to 97% to 512K 97.5% and you never get to 100% cache hit rate until your cache is the same size as main memory. So I expect they will make a will try to keep the cache as small as they can so they get the east benefits and only go to larger cache once they go to 0.18 as a balancing act between yield and size?>

I don't think AMD will even attempt to put any L2 cache on the K7 die before 0.18 micron. The K7 die is already big enough as is. That's one reason why they're going with a Slot A form factor, so that they can move the L2 cache onto the daughtercard.

As for the size of the on-die L2 cache, I chose 512K for the K7 because the K7 already has 128K of L1 cache. A good rule of thumb is to make sure your L2 cache is at least four times the size of the L1 cache, or else the L2 cache becomes useless. That's why Celeron has only 128K of L2 cache, while AMD has to add 256K to the K6-3. The Celeron core has 32K of L1 cache, while the K6 core has 64K of L1 cache.

<As you say they are both bumping into absolute limits and each new gain is smaller and this leads to commoditization. What's next?, copper? Gallium Arsenide?>

I already have a few predictions for the next big thing. AMD could integrate the memory controller right into the processor core of a future K8, just like Digital is doing for 21364. This will tremendously reduce the latency to memory.

Intel also has a few tricks up their sleeve for the Willamette core. Without revealing too much, all I can say is that there are some wacky new ideas being implemented in Willamette.

Tenchusatsu
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