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Politics : Formerly About Advanced Micro Devices
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To: Bill Jackson who wrote (44267)12/29/1998 5:25:00 PM
From: Tenchusatsu  Read Replies (2) of 1572605
 
<This would allow pure risc code to run fast and x86 to get decoded.>

It's not that simple. The P6 and K6 translates x86 instructions into what they call u-ops and r-ops, respectively. These r-ops (to take AMD's terminology) aren't exactly RISC instructions, since even RISC instructions need to be decoded (but it's much easier to decode RISC instructions than x86). Rather, the r-ops are in an internal format which is optimized and architected to work inside the CPU's state machines. Think of these r-ops not as a RISC instruction set, but rather as a medium for decoding x86 instructions into something more manageable for the CPU.

Your question is a good one, however. One of my old roommates was wondering the exact same thing when he first heard about the P6 architecture, whether you can just feed it RISC instructions and get rid of the x86 baggage altogether.

Tenchusatsu
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