Bill, what you are hoping for are continual extensions to the x86 ISA (instruction set architecture) that can transition the whole world to something more cleaner. But every extension to the x86 ISA is either going to be restricted by the x86 baggage, or is going to be incredibly hard to validate because of the infinite amount of corner cases to investigate. That's one reason why KNI looks rather limited compared to AltiVec for the PowerPC; Intel still has to work within the limits of the x86 world.
Intel chose to go the other way with Merced and IA-64. Instead of starting at the x86 ISA and decide on how to extend it, Intel started with a totally new ISA called EPIC, then worried about translating x86 instructions to IA-64. Such a move may sound rather complicated, and it is, but in one of those Merced die photos with a diagram overlay, the x86 translation unit was shown to be surprisingly small compared to the rest of the chip.
To answer your second question, whether KNI will be RISC or not, that's hard to say because it's hard to define what exactly is "RISC-like." KNI does add 8 new 128-bit registers, a move that Microprocessor Report described as "about time," but even with this, RISC architectures still have more registers. KNI adds cache-streaming instructions which allows the processor to start fetching data several cycles before it's actually needed. This sort of cache-streaming and prefetching is one key feature of advanced RISC architectures, and IA-64 will be featuring it too. The main feature of KNI, SIMD for floating point, could be considered either CISC or RISC, depending on whose philosophy you go by. It can't be RISC, since SIMD is rather specific in purpose, but it can't be CISC either, since that would imply that SIMD is rather complicated to decode, which it isn't (relative to other CISC-style instructions).
The line between CISC and RISC was blurred a while ago, which is why the old "CISC vs. RISC" debate died out then.
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