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Technology Stocks : Xilinx (XLNX)
XLNX 194.920.0%Feb 14 4:00 PM EST
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To: Hawk River Trading who wrote (2165)12/31/1998 5:27:00 AM
From: Bilow  Read Replies (1) of 3291
 
Hi all;

Got my first block of logic tested and routed, and it fits beautifully.

The DSP algorithm is 48-bits wide, and 8 stages deep. It clocks nicely at the target frequency, which is close to the ripple carry time for that width of adder in the speed grade I am using.

But the thing I liked about it was how few routing channels ended up being used. The block has close to 400 flip-flops, and the utilization is 100% over that part of the die. But I only used about 1/4th of the routing channels.

It is clear to me that the Virtex is intended to target machine placed designs. I would imagine that VHDL and Verilog designs would get pretty good utilization with that ratio of routing resources to logic, even with a mediocre floor planning. A guy who hand places his data paths, like me, is going to get phenomenal utilization.

I'm going to try and upgrade to Foundation 1.5i, in the hopes that this will cure my little problems with the mapper, which continue to dog me.

-- Carl

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