I think VHDL-to-gate mapping is a function of the synthesis tool. An increment or an "add 1" look the same in VHDL.
count <= count + 1;
The synthesis tool initially sees the statement as addition and it probably has a pretty good adder recipe. It does optimize for the constant using VCC and GNDs, but there isn't any competitive reason for the synthesis guys to go further, yet. In time, the synthesis tools will get smarter just like compilers get smarter. Someday "add 1" will implement as a counter.
CB16CE is a soft macro (I think) and Xilinx wants to maintain placement freedom. I'll bet that's why they deliberately avoid placement constraints, like carry.
Anyway, welcome to the dark side. I gave up almost all schematic entry about 18 months ago. Yes, I did fall back once to RLOCs with a 32 x 2 40 MHz mux (4062xl-1) late last year, but I think my overall productivity has increased with VHDL.
Your DSP designs sound interesting. I used to do arithmetic in MSI but the algorithms moved into processors, so now I do mostly mux/demux, serial/parallel, rate buffering, and interface functions. There is some interesting FPGA DSP IP out there now and I hope to someday get a crack at it.
By the way, we use Visual_hdl for entry and functional simulation, Synplify for synthesis, Mentor DA for schematics (sparingly) and Mentor Quicksim (ModelSim soon) for timed simulation - and M1.5.
Stan |
