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Politics : Formerly About Advanced Micro Devices
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To: Scumbria who wrote (45574)1/12/1999 2:17:00 PM
From: Tenchusatsu  Read Replies (1) of 1573683
 
Scumbria, from the INTC thread:

<No, my hope for K7 is based on the fact that it was intentionally architected for high clock rates. The 3-cycle L1 cache is a good example.>

Are you sure that the oversized L1 cache on the K7 has a latency of three clocks? How do you know this?

If that's the case, I wonder if that oversized L1 cache is going to be more of a liability than an asset to the K7. Even if it drastically reduces the amount of L1 misses, the slowness of L1 hits could be a problem. In comparison, I would guess that the P6's L1 cache hit latency is only one or two clocks, and the P6's pipeline is slightly longer than even the K7's.

Anyone care to comment?

Tenchusatsu
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