Re: "Even more, sorry to disappoint you, but
speaking in terms of bus requests etc.,
the Pentium Slot bus runs at HALF of the
rated frequency! The matter is that your
bus uses co-called "Latched Bus Protocol"
for all control and address signals.
This means that these signals have to be
asserted ONE FULL CLOCK before they
are sampled by receiver, or the sampling
cannot go every clock on these lines!"
Ali, is see no logical connection between your assertion and your explanation. Time moves in the forward direction so for a synchronous bus there is no other way for data to be sampled on a clock edge unless it was asserted on the previous clock by the transmitting agent, so what's the big deal? In addition, in a split transaction bus, the transactions are queued up and data transfers at the full frequency of the bus, not one half as you stated. Where do you get this nonsense?
Re: "Yet more, some signals like HIT#, HITM#,
BNR#, AERR#, BERR# are specified to
have TWO CLOCKS OF SETTLING TIME "before
they may be safely observed" (P.3-3),
or at 1/3 of the rated FSB speed!!! "
So what? With a pipelined bus they can be asserted 2 clocks early, so again, what's the big deal?
I see you are unaware of the chipset architecture. The 2 Xeon systems are based on the 440GX chipset which does not use the ECC signaling features of the Slot2 bus.
EP |
