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Politics : Formerly About Advanced Micro Devices
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To: Ali Chen who wrote (45653)1/12/1999 10:55:00 PM
From: Elmer  Read Replies (1) of 1573822
 
Re: "I twist nothing. The old synchronous bus
technology just does not work at high frequencies
at full speed. That's why the FULL CLOCK setup time
is necessary to make it work.
Once again: the same control/address signal
on Pentium-II bus cannot switch at every
clock as the definition of a "full" clock
rate would require; it can be changed at the second
clock only, or TWO TIMES SLOWER than the clock
rate. Therefore I coin it as 1/2 bus speed. "

Ali, your nonsense isn't fooling anybody. What other transaction type are you proposing, asynchronous? Get a clue. The P6 bus requires about 3ns setup time and less than 1ns hold, not the "full clock" that you mistakenly claim through your confused fog. The bus architecture allows for easy scaling to higher frequencies, and will go FAR higher than the 133mhz suggested for the upcoming "Camino" chipset. The P6 bus certainly can switch on every clock that matters, when it's transferring data. The notion that it is a "half speed" bus is a "half witted" notion. You also fail to grasp the concept that the P6 bus architecture was designed for SMP. The reason there are at times delays between control signals is because the processor does not own the bus after issuing a transaction request. What seems like a dumb idea to your simple mind is the whole beauty of the split transaction bus. Multiple requests can be posted from multiple agents and they can be serviced out of order. None of this is possible if an agent camps on the bus. There is a reason for all this Ali and the SMP server world is far more in touch with it than you are. That's why Xeon based servers are taking the server market by storm and you are still babbling about full clock setups and half speed busses. Ask your technician friends to explain it to you. They obviously must have a better grasp than you do.

EP
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