Formerly About Advanced Micro Devices Message Board

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Politics : Formerly About Advanced Micro Devices

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To: Ali Chen who wrote (45669)	1/13/1999 4:22:00 AM
From: Tenchusatsu	Read Replies (1) of 1573823

Elmer: <The P6 bus certainly can switch on every clock that matters, when it's transferring data.> Ali: <No kidding, in data phase. But not in the arbitration/request phase.> Request phase too, Ali. The request phase is two clocks long. This means that the request information is switched on both clocks without a turnaround cycle in between. Ali: <Yes, until the request phase is shorter than data phase (4 data clocks at least), this limitation of ONE request per THREE clocks (see Tench post) does not matter and is not a bottleneck, so who cares how far in advance those signals must be asserted. However it may change in case of double-pumped data: the slow control bus may become a bottleneck.> Well, there's two ways to solve this problem. Either double the cacheline size, or reduce the number of clocks between requests to two. Anyway, we've killed this topic many times over. Tenchusatsu

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