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Politics : Formerly About Advanced Micro Devices
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To: Kevin K. Spurway who wrote (45718)1/13/1999 4:33:00 PM
From: Scumbria  Read Replies (2) of 1571904
 
Kevin,

Here is my most likely scenario:

At the time the K6-3 concept was conceived, their speed goal was probably about 350 MHz. They probably architected the L2 latency for 350 MHz. Subsequently, Intel raised the MHz bar and the cache couldn't keep up.

I have seen this scenario dozens of times in CPU designs, where a 2% architectural performance feature is added at a 15% clock speed cost. Most CPU architects tend to be very learning challenged when it comes to architectural performance vs. clock speed trade offs.

Scumbria
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