Thank you Z, your data indicates to me that Korean chip sizes reduction are, in fact, lagging. But I have seen those numbers already and that was why I made the statement. But you only gave the Samsung chip size which is definitely not the whole picture. If you have the data, you will notice that LG & Hyundai's chip sizes are both above 100mm2. The Japanese can design smaller die sizes but the Koreans are having difficulties.
The problem is that your figures are not really an accurate assessment of the market. In fact you have neglected to include NEC's chip size, LG & Hyundai (remember, they are still separate entities), Hitachi and Mitsubishi Electric all of which have volume output each in excess of 3m units/month. Numbers for their own sake may impress some, but not me. BTW, Fujitsu will withdraw from DRAM at the end of this year.
MU has a technological edge by their ability to shrink, not the technological edge overall. The Japanese and Koreans follow a different business model by ramping up next generation chips and gaining profits from higher prices before crossover occurs. They are better than MU in doing this. Further alot depends on how successful MUs use of PSM will be in the current shrink.
I didn't understand your point on trench versus stack. Trench will allow Toshiba to shrink rapidly to 0.18, at least on par with MU. Their chip sizes are smaller than MU's at each design rule and yields above 80% in their Yokkaichi fab on their 0.22 lines with a 50mm2 chip (smaller that MU's 55mm2). Their 64meg at 0.18 will be 30mm2. Successful to say the least.
BTW, your statement: "The accounts for less than 15% of the market." This sentence makes no sense, please clarify.
BTW, In my previous post I asked if you had wafer starts and yields at the Koreans producers. If you have them you will find out that their production volumes are overly optimistic. I just hope that you are not being deceived by superficial analysis.
|
