Lattice adds memory modules to PLD family.
(Lattice Semiconductor's ispLSI/PLSI 6192XX in-system complex programmable logic devices)
(Product Announcement) Electronic News (1991), March 11, 1996 v42 n2107 p52(1). Mag. Coll.: 83A6343. Bus. Coll.: 92Y3131. Elec. Coll.: A18096009.
Abstract: Lattice Semiconductor recently introduced its ispLSI/PLSI 6192XX line of in-system programmable (ISP) complex programmable logic devices (CPLDs). The ispLSI 6192FF features two-port FIFO memory, the ispLSI 6192DM includes dual-port RAM and the ispLSI 6192SM includes single-port RAM. The devices integrate register/counter modules and dedicated memory with general-purpose programmable logic in a 25,000-gate device. Lattice is attempting to maintain high integration density and flexibility while optimizing individual block performance by integrating special-purpose and universal functions. Further, the devices feature 24 twin generic logic blocks and a 4Kb memory module. The devices feature a fixed architecture with three memory variations, distinguishing the line from other modular offerings.
Full Text:
-Laying another brick in its strategy to migrate its product portfolio from the low-density programmable logic device (PLD) market toward the higher-margin, higher-density products, Lattice Semiconductor introduced a family of high-density, in-system programmable (ISP), complex programmable logic devices (CPLDs). The company also released further details of its roadmap for 1996 product introductions. The three devices in the ispLSI/PLSI 6192XX modular PLD family differ only in their memory module architecture: the ispLSI 6192FF incorporates a two-port FIFO memory, the ispLSI 6192DM includes a dual-port random access memory (RAM), and the ispLSI 6192SM integrates a single-port RAM.
The PLDs integrate general-purpose programmable logic with dedicated memory and register/counter modules in a 25,000-gate device. By combining universal and special-purpose functions on a single device, the company is attempting to optimize individual block performance while maintaining very high integration density and functional flexibility. Each of the devices contains 24 twin generic logic blocks (twin GLBs) that provide 192 macrocells of general-purpose programmable logic, along with a 4-kilobit optimized memory module and a programmable register/counter module optimized for read/write register, shift register, counter and timer functions. Stan Kopec, Lattice's director of marketing, said the architecture in the ispLSI/PLSI 6192XX family is the same as is used in Lattice's existing 3000 series family with added memory. Both families use the twin GLB architecture. In an interview, Mr. Kopec admitted that Lattice isn't the first high-end PLD maker to announce chips with memory on-board. "There have been a couple of FPGA (field programmable gate array) manufacturers that announced devices with memory capability. Xilinx is using SRAM logic cells for memory--a distributed memory approach. Altera's 10K series comes with basic block memory. What we've done is take a CPLD architecture and develop optimized memory and logic modules that we can add to the general purpose CPLD architecture." He also revealed that Lattice is planning to introduce additional devices later this year as it drives into the higher-density market. "As of last quarter we are now about 36 percent high density and two-thirds simple PLDs, and that ratio continues to swing toward the high density side. The 25,000-gate part is the highest density part we've got in the market today," Mr. Kopec said, adding "We are working on other devices that will exceed this number and later this year you will see these higher density parts come to market."
The in-system programmable ispLSI and traditionally programmed pLSI 6192FF, 6192DM and 6192SM are currently sampling in 208-pin metal quad flat pack (MQFP) packages, with production quantities slated for 2Q96 priced at $125.75 for the 6192FF and 6192DM, and $120.50 for the 6192SM in quantities of 1,000 units. In addition, Lattice offers an entry-level set of design tools for $795 and an optional pDS+ Fitter that typically costs $1,495. Although Lattice's ispLSI/PLSI 6192XX family is called the modular PLD family, it is actually a fixed architecture with three memory variations, unlike other customizable approaches. "It is a performance and flexibility trade-off," Mr. Kopec said. "There is no question the Xilinx approach gives you more memory. The access time for the memory can vary quite widely and you can't get nearly the performance we can. In our approach we have added built-in control logic for FIFO and dual-port memory alongside the memory." The devices, packaged in 208-pin feature 96 general purpose I/O pins, 31 memory interface pins and 24 register/counter interface pins. The general purpose PLD section of the ispLSI 6192 devices supports up to 70MHz system operation with 15 nanosecond pin-to-pin (tPD) delays. All logic and memory functions are interconnected by a programmable global routing pool (GRP) that gives only a 2ns signal delay between any two functional blocks on the device.
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Perhaps, this new product line will help Lattice continue to gain a larger share of the High Density PLD market from Xlynx and Altera in the near future. Last year our High Desity line accounted for 23% of our total sales. According to this article, we are now at 36% of our sales and the company wants to expand this more for 1996.
If Lattice can implement this strategy, continue to see total sales grow with profict margins expanding as our sales mix shifts to higher margin products. The relative PE for Lattice should begin to increase and become similar to Altera and Xlynx.
EKS |
