SI
SI
discoversearch

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor.  We ask that you disable ad blocking while on Silicon Investor in the best interests of our community.  If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.
Politics : Formerly About Advanced Micro Devices
 Public ReplyPrvt ReplyMark as Last ReadFilePrevious 10Next 10PreviousNext  
To: Scumbria who wrote (46755)1/20/1999 4:48:00 PM
From: Paul Engel  Read Replies (3) of 1572470
 
Scumby - Re: "Are we forgetting the 128K L1 on K7? "

No, WE ARE NOT FORGETTING IT.

Remember - this is a SPLIT cache - 64K Data and 64K Instruction.

For most applications, this will require going OFF CHIP to the L2 cache quite frequently - for EITHER DATA OR INSTRUCTIONS OR BOTH.

The performance penalty for going off chip to a 166 or 200 MHz L2 cache - including all the latencies - will be detrimental to the K7's performance.

The K6-3, on the other hand, will have 262 K of COMBINED L1 and L2 cache - all of it ON CHIP running at full CPU speed.

Paul

Paul
Report TOU ViolationShare This Post
 Public ReplyPrvt ReplyMark as Last ReadFilePrevious 10Next 10PreviousNext  

HomeMailHotSubjectMarksPeopleMarksKeepersSettings
Terms Of UseContact UsCopyright/IP PolicyPrivacy PolicyAbout UsFAQAdvertise on SI
© 2025 Knight Sac Media.  Data provided by Twelve Data, Alpha Vantage, and CityFALCON News