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Politics : Formerly About Advanced Micro Devices
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To: Scumbria who wrote (47706)1/28/1999 6:24:00 PM
From: Tenchusatsu  Read Replies (1) of 1571172
 
<Longer latency dram access.>

Huh? The P6 bus has nothing to do with DRAM latency. As soon as the first clock of the request phase is seen, the chipset initiates the access to DRAM. I would imagine that for single processor systems, there is no arbitration phase because the single processor simply parks on the bus and keeps possession.

The only way the Super 7 platform can achieve lower latencies is via the motherboard SRAM cache. No P6 bus motherboards have any SRAM cache, though I can't think of a reason why they can't have one besides the lack of necessity.

Tenchusatsu
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