Report on Rambus Annual Meeting 1/29/99 - Part 2
1. SDRAM, SLDRAM, DDR are irrelevant to RDRAM's future - they are low performing stopgaps, that have never been realized in actual systems, and any such systems will cost more to manufacture than RDRAM-based systems in actual practice. Example: an RDRAM-based DTV would cost less than its SDRAM/DDR equivalent SDRAM/DDR/SLDRAM's best measured performance falls below that of Rambus first version. More entities are sampling RDRAMs than DDRs, and only RDRAM systems have actually worked.
2. From the fabs' point of view (they pay the royalties) Rambus' target is for a 10% cost differential per chip, in volume production.
3. Markets for RDRAM: PC/Main Memory/Graphics - 54%
WS/Servers/Net Computers - 24%
Communications: IP Switches/Fibre Channel/ATM - 8%
Consumer: Game Consoles/Set Top Boxes/DTV - 6%
Other: Copiers/Printers etc. - 8%
4. Most PC uPs will have 2 DRDRAM channels (currently 1.6 GHz capability)
Cyrix's M3 uP will have on chip interfaces for 3.2 Ghz capability
Digital's Alpha EV7 uP will have RDRAM interfaces for 6.4 GHz capability.
5. Intel is the most important partner at present, with ~80% of the uP market. To Tate's knowledge "the program is on track" (I believe that is an accurate quote in my notes). Intel developers Forums are often occasions for new product announcements. The next one is in the US 2/23/99.
6. Tate was not in a position to speculate on exact dates, but was confident RDRAM will be in mass production in 1999.
7. Rambus expects to have virtually 100% of the low end and commercial PC market, and only cede some share to DDR/SLDRAM in Servers and Workstations.
8. Rambus technology is chip-to-chip interface technology - for some time to come, RIMMs will need both RDRAM and RAC chips, both generating royalties to Rambus. The higher percentage rate RAC royalties will generate the greater fraction of royalties in small systems, and the smaller fraction in large systems.
9. Timing of royalty inflows (PCs): royalties are payable in the quarter following chip shipment by the fabs (avg 6 week delay), but chips usually will go through RIMM manufacturers (avg 2 week delay). So ~avg 2 month delay from chip shipment to Rambus getting paid.
10. The primary timeline bottleneck at present is the intro of the Intel's Camino chipset. Intel's history is not to admit even to the existence of a chipset until it is ready to ship. Boxmakers also have no interest in premature announcements that kill sales of current models. Thus the most likely scenario is almost simultaneous announcements by Intel of whatever they call Camino, and DELL, Compaq, et al of the new generation of 800MHZ computers (if not faster). (By now, I hope it has become self-evident that the idea that Tate is at liberty to say anything about this matter is ludicrous).
11. With regard to a potential threat uP chips with integrated DRAM - i.e. no need for chip-to-chip interfacing - Tate opined that it would be at least 10 years before this could become practical.
12. The company has accumulated $91 million in cash, and has not evolved any plans to use it! They have made two minimal investments - one in Interactive Silicon (my personal guess is as much to keep an eye on what they are doing, as anything).
13. An important detail about the Intel warrants is that they are only exercisable after two consecutive quarter where RDRAM-capability constitutes >=20% of Intel's uP sales. This means, that the accounting charge will only occur when Rambus'c earnings have reached a level where this necessary maneuver will be insignificant.
14. In sum - the story is intact. The ramp-up is under way. If Intel experiences technical hitches along the way (remember the over-heating problem?) - well that happens all the time. Can't we wait another month or two while they iron it out - if there indeed is a hitch?
Regards - Bernard
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