This passage from the adtn link looks good to me:
"The attraction over the longer horizon is that we get more bandwidth per pin," Allen said. "Compared to 100-MHz SDRAMs, we need only half the number of pins, and the Rambus approach delivers eight times more total bandwidth."
The current 440 LX chip set from Intel, which supports today's 66-MHz SDRAMs, requires 492 pins. Allen said the Rambus approach requires about 75 pins to implement a 1.6-Gbyte/s channel, and "we are within the pin budget to add another channel."
Also, Allen said the use of FR4 materials for the demonstration board, and the use of cost-effective 5-mil lines and spacings, will translate into system-level savings.
"With SDRAMs running at 100 MHz, we get about 100 Mbits per signal pin, or 800 Mbytes of bandwidth," Allen said. "We think that with SDRAMs, effective bandwidth is limited to 40 percent, compared with about 90 percent for Direct Rambus DRAMs. So moving to Rambus is a fairly good next step."
------------------------------------------
i.e. faster, lower pin count, and lower system cost
Bernard
|
